Flash Memory Conductive Plug Formation Preventing Etching Residue
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Solution Overview
Problem
In semiconductor device manufacturing, especially for flash memory embedded in logic circuits like FPGAs, the process of forming conductive plugs to monitor breakdown voltage of tunnel insulating films is challenging due to the need for precise contact with floating gates without short circuits, and existing methods can result in device failures from etching residues and silicide layer stripping.
Innovation Solution
A semiconductor device structure and manufacturing method involving a specific resist pattern design to prevent etching residue formation, where the first resist portion of the second resist pattern covers the thick portion of the second insulating film, and the second window of the third resist pattern is sized to encompass the contact region, ensuring the conductive plug is electrically connected to the contact region of the conductor without generating etching residue or silicide layer stripping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etching process is used to form conductive plugs, then the plugs can be formed to contact the floating gate, but etching residues are generated causing device failures and short circuits
Solution Approach 1:
The patent applies preliminary action by forming a silicide layer on the floating gate before the etching process. This pre-formed silicide layer serves as a protective mask that prevents etching residues from forming during the conductive plug formation process, thereby eliminating the harmful effect while maintaining precise contact
2Ease of manufacture
If wet processes are used in manufacturing, then cleaning and processing can be performed, but silicide layers are stripped causing device failures
Solution Approach 1:
The patent applies beforehand cushioning by forming a protective oxide film over the silicide layer before wet processing steps. This oxide film acts as a cushioning protective layer that prevents the silicide layer from being stripped during wet cleaning processes, while still allowing necessary manufacturing operations to proceed
3Device complexity
If the resist pattern is not optimized, then the manufacturing process is simpler, but etching residues form at the contact region
Solution Approach 1:
The patent applies local quality by designing a resist pattern with different characteristics in different regions: a first resist portion with specific dimensions and properties for the contact region, and a second resist portion for other areas. This localized optimization prevents etching residues at the critical contact region while maintaining overall process feasibility
Data Source
AI summary
Disclosed is a method of manufacturing a semiconductor device, including the steps of: forming on a second insulating film a first resist pattern having a first window; employing the first resist pattern as an etching mask to form first openings exposed from contact regions CR; forming, on a second conductive film, a second resist pattern having first resist portions; employing the second resist pattern as an etching mask to form first and second conductors, a floating gate and a control gate; forming a third resist pattern in regions I, II and III; and employing the third resist pattern as an etching mask to remove the portions of the second conductors under second windows.