Flash Memory Polling Time Adjustment for IOPS Optimization
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Solution Overview
Problem
In data storage devices with flash memory, the inefficiency of status polling for determining if a die is busy leads to resource wastage and performance issues due to either excessive polling requests or prolonged waiting times, especially as device size increases and dedicated pins become impractical.
Innovation Solution
Logical grouping of flash memory portions based on Program/Erase cycles and physical location allows for tailored polling times to be set, adjusting initial and interval polling times based on monitored command performance latency to optimize resource usage and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If polling times are too short, then the controller can quickly determine if the die is ready, but resources are wasted with excessive polling requests and bus traffic
Solution Approach 1:
The patent implements dynamic polling time adjustment where the controller adapts polling intervals based on die status and command types. The system transitions from fixed polling to variable polling times, optimizing the balance between quick status detection and resource conservation by adjusting polling frequency according to actual die availability and operation complexity.
Solution Approach 2:
The controller modifies polling time parameters based on monitored command performance latency and die readiness patterns. By changing the polling time parameter dynamically rather than using a fixed interval, the system achieves faster response when needed while reducing excessive polling during normal operations, thereby conserving resources.
2Loss of energy
If polling times are too long, then resource usage is reduced, but the efficiency and performance of the flash memory is wasted due to delayed command execution
Solution Approach 1:
The system employs dynamic polling time adjustment that responds to die status and command characteristics. When the die is ready or commands are simple, polling intervals are extended to conserve resources. When commands are complex or the die is processing, polling intervals are shortened to maintain high productivity and prevent wasted memory efficiency.
Solution Approach 2:
The controller adjusts the polling time parameter based on monitored command performance latency and die readiness patterns. By dynamically changing this parameter, the system optimizes the trade-off between resource conservation and maintaining high flash memory throughput and IOPS performance.
3Measurement precision
If dedicated pins are used to determine die availability, then the controller can immediately know if the die is ready, but the device becomes impractical as size increases with more NAND flash dies due to insufficient pins
Solution Approach 1:
The patent extracts the die availability detection function from dedicated physical pins and implements it through software-based status polling over the memory bus. This removes the constraint of requiring one pin per die, allowing the system to scale to multiple dies without proportionally increasing pin complexity.
Solution Approach 2:
The memory bus serves as an intermediary for status communication between the controller and multiple dies. Instead of direct pin-to-die availability signaling, the controller uses the shared memory bus to poll status registers, enabling scalable die detection without increasing physical connection complexity.
Data Source
AI summary
A Data Storage Device (DSD) includes a flash memory for storing data. Portions of the flash memory are grouped into logical groups based on at least one of a number of Program/Erase (P/E) cycles and a physical level location of the portions of the flash memory. A command performance latency is monitored for each logical group, and at least one polling time for each respective logical is set based on the monitored command performance latency for the logical group. The at least one polling time indicates a time to wait before checking whether a portion of the flash memory in the logical group has completed a command.