Flash Memory Floating Gate Polysilicon Grain Control
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Solution Overview
Problem
Existing flash memory devices face challenges in achieving uniform charge distribution in floating gates due to non-uniform polysilicon grain sizes, which limits their storage capacity and requires strict manufacturing criteria for forming thin, discontinuous or coarse polysilicon layers.
Innovation Solution
A method involving the formation of silicon seed crystals and polysilicon layers using nitrogen or oxygen atmosphere gases, followed by annealing processes, to create a uniform distribution of small grain sizes in the polysilicon layers for improved charge distribution, including the formation of gate insulating layers, silicon seed crystals, undoped and doped polysilicon layers, and annealing steps to achieve a smooth and continuous thin film.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the undoped polysilicon layer is formed as thin as possible (100 Å or less) to reduce grain size and improve charge distribution, then the charge distribution of the floating gate is greatly improved, but the polysilicon layer is grown in the form of an island to form a discontinuous thin film or a continuous thin film with a very coarse surface
Solution Approach 1:
Silicon seed crystals are formed on the gate insulating layer surface before forming the undoped polysilicon layer. These pre-formed seed crystals serve as nucleation sites that guide the subsequent polysilicon deposition, ensuring uniform grain distribution and fine grain size even at thin film thicknesses of 100 Å or less, thereby preventing island formation and surface coarsening
Solution Approach 2:
The patent changes the deposition parameters by controlling the ratio of silicon source gas to nitrogen or oxygen atmosphere gas (1:10 to 1:1), and by performing in-situ annealing with N2O or NO gas. These parameter changes enable the formation of continuous, smooth polysilicon films with fine grain structures at thicknesses of 100 Å or less, resolving the contradiction between thin film formation and surface quality
2Quantity of substance
If a polysilicon layer with uniform grain distribution and small grain size is formed to satisfy strict charge distribution criteria for multi-level cell flash memory, then the storage capacity is increased to 2 to 4 bits per cell, but the manufacturing process becomes more complex and requires precise control of deposition and annealing parameters
Solution Approach 1:
The patent combines multiple processes into integrated sequences: silicon seed crystal formation and undoped polysilicon layer deposition are performed in-situ without breaking vacuum; annealing is performed in-situ using N2O or NO gas. This merging of processes achieves the complex manufacturing requirements for high-capacity flash memory while streamlining the overall fabrication sequence
Solution Approach 2:
The patent uses nitrogen or oxygen atmosphere gases during deposition and N2O or NO gas during annealing to create controlled inert environments. This prevents unwanted chemical reactions and ensures uniform polysilicon film formation with fine grain structures, enabling multi-level cell fabrication without requiring additional complex equipment
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the charge distribution characteristics of the floating gate, improves electrical properties, and enables the integration of multi-level cells with 2 to 4 bits without requiring additional equipment, thereby increasing storage capacity and design integration.
Implementation Method 1
forming silicon seed crystals on a surface of the gate insulating layer by reacting a nitrogen or oxygen atmosphere gas and a silicon source gas
Implementation Method 2
forming an undoped crystalline polysilicon layer by crystallizing the undoped amorphous polysilicon layer
Implementation Method 3
An annealing process is performed in-situ using an N2O gas or an NO gas on the gate insulating layer
Implementation Method 4
forming silicon seed crystals on a surface of the gate insulating layer by reacting a nitrogen or oxygen atmosphere gas and a silicon source gas
Data Source
AI summary
A method of manufacturing a flash memory device comprises forming a gate insulating layer on a semiconductor substrate, forming silicon seed crystals on a surface of the gate insulating layer by reacting a nitrogen or oxygen atmosphere gas and a silicon source gas, forming a first layer for a floating gate over the gate insulating layer and the silicon seed crystals by increasing an amount of the silicon source gas, and forming a second layer for a floating gate on the first layer for a floating gate.