Flash Memory Coupling Capacitance via Vertical Polysilicon Spacers
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Solution Overview
Problem
The reduction in size of flash memory units leads to decreased programming efficiency due to reduced voltage coupling from the source terminal to the floating gate, and increased resistance in the source polysilicon wire, which complicates manufacturing and increases costs.
Innovation Solution
The implementation of a self-aligned split gate flash memory structure with extended polysilicon spacer regions from the central part of the source region, where the insulating material between the spacer region and the floating gate has a predetermined thickness of 1 nm-100 nm, composed of silicon oxide and nitride layers, to increase coupling capacitance and voltage coupling to the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If the minimum size for photolithography and the dimension of elements are reduced to manufacture more flash memory units within the same area, then the integration is improved, but the voltage coupled from the source terminal to the floating gate is decreased and programming efficiency is reduced
Solution Approach 1:
The source polysilicon region is extended in the vertical dimension above the floating gate, transforming a two-dimensional planar structure into a three-dimensional structure. This vertical extension increases the overlapping area between the source polysilicon and the floating gate without increasing the planar footprint, thereby maintaining voltage coupling and programming efficiency while achieving higher integration density.
Solution Approach 2:
The source polysilicon region is positioned to vertically cover and overlap with the floating gate, creating a nested configuration where one structure is partially contained within the vertical space of another. This nesting increases the effective coupling area without requiring additional lateral space, resolving the contradiction between miniaturization and programming efficiency.
2Reliability
If the size of the source diffusion region is reduced to prevent channel breakdown, then the reliability is improved, but the voltage coupled from the source terminal to the floating gate is decreased
Solution Approach 1:
By extending the source polysilicon vertically above the floating gate, the invention compensates for the reduced lateral size of the source diffusion region. The vertical extension provides additional overlapping area with the floating gate, maintaining the voltage coupling necessary for programming while the reduced lateral dimensions prevent channel breakdown.
Solution Approach 2:
The source polysilicon structure is made non-uniform with different dimensions at different locations: the lateral size is reduced at the diffusion region level to prevent breakdown, while the vertical height is increased above the floating gate to maintain coupling. This local variation in geometry allows simultaneous achievement of reliability and programming efficiency.
3Area of stationary object
If the size of the source polysilicon is reduced, then the integration is improved, but the resistance of the source polysilicon wire is increased and reading current is reduced
Solution Approach 1:
The source polysilicon is extended vertically to create a three-dimensional structure that reduces lateral dimensions for higher integration while maintaining or reducing overall resistance through the vertical conduction path. The increased vertical height provides additional cross-sectional area for current flow, compensating for reduced lateral dimensions.
4Productivity
If a second control gate is added above the floating gate to keep programming efficiency, then the programming efficiency is maintained, but the complexity in circuit design and manufacturing process is increased and manufacturing cost is increased
Solution Approach 1:
The invention extracts the voltage coupling function from the control gate and relocates it to the source polysilicon structure. By extending the source polysilicon vertically above the floating gate, the source itself becomes the element that provides strong coupling, eliminating the need for an additional control gate and simplifying the overall device structure.
Solution Approach 2:
The source polysilicon structure is given multiple functions: it serves as the source terminal for carrier injection, provides voltage coupling to the floating gate through vertical overlap, and acts as a conductive path for reading current. This multi-functionality eliminates the need for separate structures like a second control gate, reducing complexity while maintaining programming efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances the coupling capacitance at the source terminal, increasing the voltage coupled to the floating gate, thereby improving programming efficiency while maintaining low production costs and simplifying the manufacturing process.
Implementation Method 1
the insulating material between the central part of the source region and the floating gate has a predetermined thickness to facilitate the voltage coupling between the central part of the source region and the floating gate
Implementation Method 2
F-N tunneling between the floating gate 12 and the control gate 11 is used for erasing
Implementation Method 3
hot carrier injection at the source terminal serves as the approach for programming. During programming, a high voltage is imposed on the source 13 to produce channeling hot carriers
Data Source
AI summary
The electrically erasable programmable memory and its manufacturing method of the present invention forms above the floating gate the polysilicon spacer regions that are extended from the central part of the source region; the insulating part between the polysilicon spacer region and the floating gate has a smaller thickness to increase the capacitance between the floating gate and the polysilicon spacer region and further increasing the voltage coupled to the floating gate. Therefore, the present invention can effectively increase the coupling capacitance at the drain terminal, and has an advantage of low cost and easy production.