Flash Memory Programming with Positive Source Bias
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Solution Overview
Problem
Conventional flash memory devices with virtual ground architecture experience excessive bitline leakage current during programming and verification operations, leading to increased power consumption and potential errors in verification measurements due to parasitic leakage current, which worsens with the number of program-erase cycles.
Innovation Solution
Implementing a method that involves applying a positive source bias voltage to a selectable bitline corresponding to the source of the target cell during programming and verification operations, which reduces bitline leakage current by establishing a reverse bias across the bitline-substrate junction, thereby controlling and minimizing leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional virtual ground architecture is used for flash memory programming, then the memory device can be programmed and verified, but excessive bitline leakage current occurs leading to increased power consumption
Solution Approach 1:
The patent applies a positive source bias voltage to the source bitline during programming and verification operations. This parameter change (applying positive voltage instead of ground or negative voltage) reverse-biases the bitline-substrate junction, reducing leakage current and thereby decreasing power consumption while maintaining proper memory operation
Solution Approach 2:
The patent preemptively applies a positive voltage to the source bitline before programming operations to prevent excessive leakage current from occurring in the first place. This preliminary anti-action counteracts the harmful leakage effect before it can significantly increase power consumption, especially important as the device ages through multiple program-erase cycles
2Measurement precision
If conventional verification operations are performed, then memory cell verification can be conducted, but parasitic leakage current causes errors in verification measurements
Solution Approach 1:
During verification operations, the patent maintains a positive voltage on the source bitline, which reverse-biases the bitline-substrate junction and minimizes parasitic leakage current. This parameter change ensures that the measured verification current accurately reflects the actual cell current without being corrupted by leakage components, thereby improving measurement precision
Solution Approach 2:
The patent effectively extracts or removes the parasitic leakage current component from the measurement by applying the positive source bias voltage. This separates the harmful leakage current from the useful verification signal, allowing for accurate measurement of only the actual cell verification current
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach conserves power by reducing bitline leakage current during programming and enhances the accuracy of verification operations by eliminating the leakage current component, ensuring more precise measurement of the actual verification current.
Implementation Method 1
applying a positive source bias voltage to a selectable bitline corresponding to the source of the target cell during programming and verification operations, which reduces bitline leakage current by establishing a reverse bias across the bitline-substrate junction
Data Source
AI summary
A flash memory system configured in accordance with an example embodiment of the invention employs a virtual ground array architecture. During programming operations, target memory cells are biased with a positive source bias voltage to reduce or eliminate leakage current that might otherwise conduct through the target memory cells. A positive source bias voltage may also be applied to target memory cells during verification operations (program verify, soft program verify, erase verify) to reduce or eliminate leakage current that might otherwise introduce errors in the verification operations.