Flash Memory Erase Control via Post-Program Voltage Verification

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Solution Overview

Problem

Conventional flash memory devices face issues with over-erased cells during post-program operations, leading to increased threshold voltages that can cause errors in read and program operations, and existing solutions do not effectively prevent this increase.

Innovation Solution

A method and device for flash memory devices that perform post-program operations with specific verify voltages to detect and correct over-erased cells, ensuring that memory cells are not over-programmed, and incorporating a control logic to manage voltage levels and verify operations to prevent threshold voltage expansion.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional erase operations are performed on flash memory devices, then memory cells are erased, but over-erased cells are created which have threshold voltages lower than the minimum erase threshold voltage

Engineering Contradiction:
Improveerase operation reliabilityVSAvoidthreshold voltage control precision
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The patent implements a feedback mechanism by performing a verify operation after the erase operation to detect over-erased cells. The control logic uses the verify result to determine whether to perform a post-program operation, creating a closed-loop control system that adjusts the erase process based on actual cell states.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies a post-program operation as a preliminary corrective action immediately after detecting over-erased cells. This preliminary action adjusts the threshold voltages of over-erased cells before they can cause problems in subsequent read or program operations.

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If post-program operations are performed to correct over-erased cells, then threshold voltage control is improved, but additional operations increase processing time

Engineering Contradiction:
Improvethreshold voltage control precisionVSAvoiderase operation time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies partial action by performing the post-program operation only on cells that are identified as over-erased through the verify operation. Instead of re-programming all cells in a block, the control logic selectively applies the post-program operation only where needed, reducing the total processing time while still achieving the desired threshold voltage control precision.

Inventive Principle:
Principle #16Partial or excessive action

3Measurement precision

If multiple verify operations with different voltages are performed, then detection precision of over-erased cells is improved, but device complexity increases

Engineering Contradiction:
Improveover-erased cell detection precisionVSAvoidcontrol logic complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the verification process into two distinct voltage levels: a first verify voltage for initial over-erased cell detection and a second verify voltage for confirmation. This segmentation allows the system to use simpler control logic at each stage rather than implementing a single complex verification mechanism, as each voltage level targets specific threshold voltage ranges.

Inventive Principle:
Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively minimizes the stress on memory cells, prevents threshold voltage increases, and enhances the reliability of read and program operations by accurately identifying and correcting over-erased cells, thereby maintaining operational integrity.

Implementation Method 1

electrons implanted on a floating gate are removed by Fowler-Nordheim (F-N) tunneling when satisfying the above bias conditions

Methodology Applied
Scientific EffectFowler-Nordheim tunneling:

Data Source

PatentUS7558122B2Flash memory device and method of erasing flash memory device
Publication Date: 2009.07.07 SAMSUNG ELECTRONICS CO LTD
  • US7558122B2 patent drawing
  • US7558122B2 patent drawing
  • US7558122B2 patent drawing

AI summary

A flash memory device and a method of erasing memory cells in a flash memory device are provided. A first post program operation is performed on erased memory cells having a threshold voltage lower than a first program verify voltage. A second post program operation is performed on erased memory cells having a threshold voltage lower than a second program verify voltage. The second program verify voltage is lower than the first program verify voltage.