Flash Memory Post-Program Verify Down-Shifting Threshold Voltage
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Solution Overview
Problem
NAND-type flash memory devices face program failures due to shifts in threshold voltage distributions caused by program disturb or stress, which are difficult to prevent with conventional post-program operations.
Innovation Solution
A driving method that increases the sensing current during the post-program verify operation by adjusting the evaluation time and voltages applied to bit lines, allowing for a down-shifted verify level and preventing program failures by positioning the right tail of the threshold voltage distribution at a voltage lower than −1 V.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional post-program operation is used, then the threshold voltage distribution is narrowed, but the right tail of the distribution shifts to higher voltages causing program failures
Solution Approach 1:
The patent changes the verify level parameter by increasing the sensing current during the post-program verify operation. This is achieved by adjusting the evaluation time and voltages applied to bit lines, which causes the verify level to be down-shifted to a lower voltage than the conventional −1 V. This parameter change prevents program failures by ensuring the right tail of the threshold voltage distribution remains below the verify level.
2Ease of operation
If the verify level is maintained at −1 V, then the post-program operation can be performed, but program failures occur when threshold voltage distribution shifts due to program disturb or stress
Solution Approach 1:
The patent implements a feedback mechanism by increasing the sensing current during the verify operation based on the actual threshold voltage distribution characteristics. The evaluation time and bit line voltages are adjusted to increase the sensing current, which provides feedback information about the memory cell state. This feedback allows the verify level to be dynamically down-shifted to prevent program failures while maintaining operation capability.
3Reliability
If the sensing current is increased during post-program verify operation, then the verify level is down-shifted preventing program failures, but the evaluation time must be shortened
Solution Approach 1:
The patent applies partial action by adjusting the evaluation time to be shorter than the standard read operation time. The sensing current is increased through adjusted bit line voltages and evaluation time parameters, allowing the verify operation to complete faster. This partial action approach prevents program failures while reducing the time loss associated with extended evaluation periods.
Data Source
AI summary
In a driving method of a flash memory device including a selected first bit line and an unselected second bit line, a program voltage of a pulse is applied to word lines of all memory cells in a block passing an erase verify operation. After the first and second bit lines are precharged to a predetermined level, a ground voltage is applied to the word lines of all the memory cells in the block. The memory cells are evaluated for a predetermined time shorter than an evaluation time of a read operation. Whether or not a memory cell passing a verify operation exists among the memory cells is sensed. Resultantly, when the memory cell passing the verify operation exists, the memory cells in the block are programmed to a desired level using a predetermined program voltage and a step voltage.