Flash Memory Power Failure Handling Circuit
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Solution Overview
Problem
Flash memory devices, particularly MLC and TLC types, are vulnerable to data damage due to power failures, as subsequent data writing can disrupt previously stored data when power is suddenly interrupted.
Innovation Solution
A flash memory device incorporating a power failure handling circuit and a capacitor that detects voltage drops, preventing further write commands and ensuring completion of data writing by supplying stored power from a capacitor during power outages, thereby protecting existing data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data are sequentially written into strong page and weak page of MLC flash memory, then data capacity is increased, but data previously written to strong page may be damaged when power failure occurs
Solution Approach 1:
The patent applies preliminary action by setting the ready/busy pin to a specific voltage level before power failure occurs. When the voltage source drops below a threshold, the power failure handling circuit proactively configures the ready/busby pin to indicate that the flash memory is busy, preventing the controller from initiating new write operations that could damage existing data. This preemptive measure ensures data integrity is maintained before the actual power failure impacts the data.
2Loss of energy
If power supplied to flash memory is suddenly turned off, then power consumption is reduced, but subsequent data writing may be halted and previously stored data may be damaged
Solution Approach 1:
The power failure handling circuit acts as an intermediary between the voltage source and the ready/busy pin. It monitors the voltage source level and mediates the signal to the controller by setting the ready/busy pin to a specific level when voltage drops occur. This intermediary function allows the system to communicate power status to the controller without requiring direct power supply to all components, thereby protecting data integrity during power transitions.
3Productivity
If controller sends second write command to flash memory during power failure, then writing speed is maintained, but data previously stored in flash memory may be damaged
Solution Approach 1:
The patent implements feedback by monitoring the voltage source level and using this information to control the ready/busy pin state. When the voltage source drops below a predetermined threshold, the power failure handling circuit detects this condition and feeds back to the controller by setting the ready/busy pin to a specific level, which signals the controller to halt write operations. This feedback mechanism prevents the controller from sending write commands during power failure conditions that could damage data, while allowing normal high-speed writing when voltage is sufficient.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents data damage from power failures by ensuring that flash memory devices can complete writing operations even during power interruptions, maintaining data integrity in MLC and TLC flash memories.
Implementation Method 1
The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.
Data Source
AI summary
A flash memory device. In one embodiment, the flash memory device includes a flash memory, a diode, a controller, and a capacitor. The flash memory has a voltage source pin. The diode is coupled between a voltage source and the voltage source pin of the flash memory. The controller is coupled to the flash memory via a data bus. The capacitor is coupled between the voltage source pin of the flash memory and a ground, and supplies power to the flash memory to enable the flash memory to complete writing of at least one data page when the level of the voltage source is lowered.