Flash Memory Power Loss Detection via Status Bit
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Solution Overview
Problem
Current algorithms for detecting asynchronous power loss in flash memory devices are complex and inefficient, leading to increased firmware complexity, cost, and premature queuing of super blocks for garbage collection, which can result in reduced memory availability and poor performance during recovery.
Innovation Solution
The method involves identifying pages affected by power loss by changing the data state of memory cells and storing a value indicating power loss without requiring margin read operations, thereby facilitating faster recovery and reducing unnecessary garbage collection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If current algorithms for detecting asynchronous power loss are used, then power loss detection capability is maintained, but firmware complexity increases and performance deteriorates
Solution Approach 1:
The patent extracts the power loss detection functionality from complex margin read operations and implements it through a simple status bit check in the overhead data. By separating the detection mechanism from the data verification process, the firmware complexity is significantly reduced while maintaining reliable power loss detection capability.
Solution Approach 2:
The overhead data structure automatically records power loss events during programming operations without requiring external monitoring. The memory device itself generates and maintains the power loss status information, eliminating the need for complex external detection algorithms and reducing firmware burden.
2Reliability
If current power loss detection algorithms are implemented, then power loss events are identified, but super blocks are prematurely queued for garbage collection reducing memory availability
Solution Approach 1:
The patent replaces the mechanical/complex process of margin read operations with a simple digital status bit check. This substitution allows for rapid power loss detection without triggering premature garbage collection, thereby maintaining memory availability while still identifying power loss events accurately.
3Measurement precision
If margin read operations are performed to detect power loss, then accurate power loss detection is achieved, but recovery time increases and performance decreases
Solution Approach 1:
The patent performs preliminary recording of power loss status during the programming operation itself, storing this information in the overhead data before any recovery operations are needed. This preliminary action eliminates the need for time-consuming margin read operations during recovery, thereby reducing recovery time while maintaining detection accuracy.
4Reliability
If complex detection algorithms are used, then power loss detection capability is maintained, but device cost increases
Solution Approach 1:
The patent changes the detection parameter from complex multi-step margin read operations to a simple status bit examination. This parameter change maintains the essential power loss detection capability while dramatically simplifying the implementation, thereby reducing device cost without sacrificing reliability.
Data Source
AI summary
Apparatus having an array of memory cells include a controller configured to read a particular memory cell of a last written page of memory cells of a block of memory cells of the array of memory cells, determine whether a threshold voltage of the particular memory cell is less than a particular voltage level, and mark the last written page of memory cells as affected by power loss during a programming operation of the last written page of memory cells when the threshold voltage of the particular memory cell is determined to be higher than the particular voltage level.