Flash Memory Power Loss Recovery via Address Extraction

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Solution Overview

Problem

In flash memory devices, unexpected power loss can lead to invalidation of the most recent mapping information and user data, causing complexity and time consumption in data recovery due to the need for power loss detection algorithms, especially as the number of memory blocks and data states increases.

Innovation Solution

The solution involves saving the address of a memory location being programmed at the time of power loss to a predetermined location within the memory, allowing for quicker recovery by programming this address and associated data to a different location, thereby simplifying the recovery process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power loss detection algorithms are implemented to handle unexpected power loss in flash memory devices, then data reliability is improved, but device complexity and recovery time increase due to the need to scan through numerous memory blocks and data states

Engineering Contradiction:
Improvedata reliabilityVSAvoidrecovery process complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by saving the address of the memory location being programmed at the time of power loss to a predetermined location within the memory before actual power loss occurs. This advance preparation eliminates the need for complex power loss detection algorithms and extensive scanning during recovery, as the system already knows where to look for incomplete programming operations. The address is stored in a dedicated recovery area that is automatically checked upon power restoration.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If comprehensive power loss detection and recovery algorithms are implemented across all memory blocks, then data reliability is improved, but the time required for recovery increases significantly

Engineering Contradiction:
Improvedata reliabilityVSAvoidrecovery time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent extracts the critical recovery information (the address of the memory location being programmed at the time of power loss) from the complex set of all memory blocks and isolates it in a predetermined location. This extraction allows the recovery process to focus only on the specific address stored in the predetermined location rather than scanning through all memory blocks, dramatically reducing recovery time while maintaining data reliability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Loss of time

If the address of memory location being programmed at power loss is saved to a predetermined location, then recovery time is reduced, but additional memory space is required

Engineering Contradiction:
Improverecovery timeVSAvoidmemory space requirement
Core Design Contradiction:
Loss of timeVSVolume of stationary object

Solution Approach 1:

The patent applies local quality by designating a specific predetermined location within the memory device to store the address of the memory location being programmed at the time of power loss. This localized storage approach uses minimal memory space (only enough to store one address) in a specific area, rather than distributing recovery information across the entire memory device. The predetermined location is optimized for quick access during recovery operations.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11328777B2Responding to power loss
Publication Date: 2022.05.10 MICRON TECHNOLOGY INC
  • US11328777B2 patent drawing
  • US11328777B2 patent drawing
  • US11328777B2 patent drawing

AI summary

Methods of operating apparatus, as well as apparatus configured to perform such methods, include checking whether power loss to the apparatus during programming of user data to a grouping of memory cells of the apparatus is indicated, and, when power loss is indicated, checking feature settings of the apparatus to determine a location of the apparatus containing an address of the grouping of memory cells, and recovering the address of the grouping of memory cells from the determined location.