Flash Memory Power Shutoff Detection and Register Reset
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Solution Overview
Problem
Existing semiconductor devices with nonvolatile memories, such as flash memory, are prone to malfunction due to momentary power interruptions, leading to abnormal rewrite voltages and erroneous writings, as they cannot detect such interruptions effectively.
Innovation Solution
Incorporating a power shutoff detection register and a control logic circuit that resets the internal register when power shutoff is detected, preventing malfunctions by ensuring accurate voltage levels and memory cell selection during data rewrite operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If momentary power interruption occurs during flash memory rewriting, then the system continues operation without detection, but the internal register and address latch circuit information becomes broken causing memory malfunction
Solution Approach 1:
The patent applies preliminary action by setting a specific initial value in the power shutoff detection register before operation. This predetermined value serves as a reference state that allows the system to detect power interruptions by comparing the current state against this pre-established baseline, enabling proactive detection before malfunction occurs
Solution Approach 2:
The patent implements feedback by continuously monitoring the power shutoff detection register and comparing its current value against the initial value. When a change is detected, the system receives feedback about the power interruption event and automatically responds by resetting the internal register, creating a closed-loop control mechanism that prevents memory malfunction
2Reliability
If the system does not detect power shutoff, then operation continues uninterrupted, but abnormal rewrite voltage and erroneous writing occur
Solution Approach 1:
The patent introduces an intermediary element - the power shutoff detection register - that mediates between the physical power shutoff event and the system's response. This register acts as a sensor that translates the abstract concept of power interruption into a concrete, measurable state change that can be detected and acted upon by the control logic
Solution Approach 2:
The patent utilizes parameter changes by monitoring the value state of the power shutoff detection register. The detection mechanism relies on detecting changes in this parameter (the register value) from its initial state to a different state, which indicates that a power shutoff event has occurred, enabling reliable detection through simple parameter comparison
3Reliability
If internal register is not reset after power shutoff, then system structure remains simple, but flash memory malfunctions due to broken high voltage level information
Solution Approach 1:
The patent applies self-service by enabling the system to automatically detect and respond to power shutoff events without external intervention. The control logic circuit autonomously monitors the power shutoff detection register and automatically resets the internal register when needed, allowing the system to service itself and prevent malfunction without requiring external control
Data Source
AI summary
In an internal register, a value for controlling operation of a flash memory is stored. A power shutoff detection register holds a value which changes when power shutoff occurs, and data stored in a specific memory cell is written in the power shutoff detection register. An EX-OR circuit compares the data stored in the specific memory cell with the value of the power shutoff detection register to thereby detect power shutoff. When power shutoff is detected, the value of the internal register is re-set. Thus, when power shutoff occurs, the flash memory can be prevented from malfunctioning.