Flash Memory Pre-compensation for Neighbor Interference
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Solution Overview
Problem
In flash memory devices, charge storage in neighboring memory cells can inadvertently change the threshold voltage of a selected memory cell, leading to misreading and reliability issues, especially when multiple neighboring cells are programmed, due to factors like capacitive coupling and temperature fluctuations.
Innovation Solution
Implementing one pass threshold voltage pre-compensation programming operations that use aggressor bits from non-selected memory cells to pre-compensate the threshold voltage of selected memory cells, employing a stepped sensing architecture with multiple verify operations to ensure accurate data state programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If charge storage structures are used to increase memory density, then storage capacity is improved, but threshold voltage stability deteriorates due to neighboring cell interference
Solution Approach 1:
The patent applies preliminary action by performing a read-disturb compensation operation before the actual read operation. The system detects potential threshold voltage shifts caused by neighboring programmed cells and pre-adjusts the sense amplifier reference voltage or applies compensating voltages to counteract the expected interference, thereby maintaining accurate data reading despite the presence of charge storage structures in neighboring cells.
Solution Approach 2:
The patent implements feedback by monitoring the actual threshold voltage of the selected memory cell and using this information to adjust subsequent read operations. The system detects the extent of interference from neighboring cells and dynamically modifies the sense amplifier threshold or applies corrective voltages based on the measured disturbance, creating a closed-loop system that maintains reading accuracy despite varying interference conditions.
2Productivity
If multiple neighboring memory cells are programmed, then memory utilization is improved, but reading accuracy deteriorates due to capacitive coupling effects
Solution Approach 1:
The patent applies preliminary action by performing a read-disturb compensation operation before the actual read operation. The system detects potential threshold voltage shifts caused by neighboring programmed cells and pre-adjusts the sense amplifier reference voltage or applies compensating voltages to counteract the expected interference, thereby maintaining accurate data reading despite the presence of charge storage structures in neighboring cells.
Solution Approach 2:
The patent applies local quality by tailoring the compensation strategy to the specific interference conditions of each memory cell being read. Rather than applying a uniform compensation approach, the system adjusts the compensation magnitude and type based on the local interference environment, such as the programming state of specific neighboring cells and their spatial relationship to the selected cell, thereby optimizing reading accuracy for each local context.
3Speed
If standard programming operations are used, then programming speed is maintained, but data state verification accuracy deteriorates under threshold voltage variation
Solution Approach 1:
The patent applies preliminary action by performing a read-disturb compensation operation before the actual read operation. The system detects potential threshold voltage shifts caused by neighboring programmed cells and pre-adjusts the sense amplifier reference voltage or applies compensating voltages to counteract the expected interference, thereby maintaining accurate data reading despite the presence of charge storage structures in neighboring cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and accuracy of data reading and writing in flash memory devices by mitigating the effects of neighboring cells on threshold voltage, reducing errors and improving overall memory performance.
Implementation Method 1
Changes in threshold voltage (Vt) of the memory cells, through programming (which is often referred to as writing) of charge storage structures (e.g., floating gates or charge traps)
Implementation Method 2
When combined with other factors, such as capacitive coupling, temperature fluctuations, program/erase cycling, and storage of multiple bits of data per memory, the influence of neighboring charge storage structures may cause a memory cell to be misread.
Data Source
AI summary
Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.