Flash Memory Read Using Predicted TVSO Values

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Solution Overview

Problem

Systems using threshold-voltage-shift read instructions for flash memory devices require background reads to identify TVSO values, consuming significant bandwidth and reducing available resources for host-requested operations while maintaining Uncorrectable Bit Error Rate (UBER) within acceptable levels.

Innovation Solution

A method and apparatus that utilize retention-and-read-disturb-compensating regression neural networks (RNNs) to predict TVSO values by storing configuration files, identifying current program and erase cycles, retention time, and read disturbs, and loading these into a neural network engine to perform predictions, allowing for TVSO value identification without background reads.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If background reads are performed to identify TVSO values, then UBER is maintained within acceptable levels, but bandwidth is significantly consumed reducing available resources for host-requested operations

Engineering Contradiction:
ImproveUBERVSAvoidbandwidth
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies preliminary action by pre-training neural networks during manufacturing to predict TVSO values based on PE cycle counts, retention times, and read disturb counts. This pre-computation eliminates the need for background reads during operation, maintaining UBER while freeing bandwidth for host operations. The neural networks are trained offline with comprehensive data, then deployed to make real-time predictions without consuming operational bandwidth.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces the mechanical/background read process with a neural network-based prediction system. Instead of performing actual read operations to measure and determine TVSO values, the system uses trained neural networks that compute predictions based on input parameters (PE cycles, retention time, read disturbs). This substitution eliminates bandwidth consumption while maintaining prediction accuracy for UBER control.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Measurement precision

If multiple TVSO values are sent for MLC, TLC, QLC and PLC flash memory devices, then accurate reads are achieved, but the complexity of the read instruction increases

Engineering Contradiction:
Improveread accuracyVSAvoidread instruction complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter representation by using a single TVSO value derived from neural network predictions based on multiple input parameters (PE cycle count, retention time, read disturb count) rather than sending multiple TVSO values. The neural network processes these parameters and outputs an optimized single TVSO value that maintains read accuracy while simplifying the instruction set for MLC, TLC, QLC, and PLC devices.

Inventive Principle:
Principle #35Parameter changes

3Reliability

If background reads are performed to identify TVSO values, then reliable read operations are maintained, but the time required for system initialization and operation increases

Engineering Contradiction:
Improveread operation reliabilityVSAvoidinitialization time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs the time-consuming work of TVSO value determination during the pre-training phase of neural network development, not during system initialization or operation. The neural networks are trained offline using comprehensive datasets that capture various flash memory conditions. Once trained, the networks instantly predict TVSO values during operation without requiring time-consuming background reads, thus maintaining reliability while eliminating initialization time penalties.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11699493B2Method and apparatus for performing a read of a flash memory using predicted retention-and-read-disturb-compensated threshold voltage shift offset values
Publication Date: 2023.07.11 MICROCHIP TECHNOLOGY INC
  • US11699493B2 patent drawing
  • US11699493B2 patent drawing
  • US11699493B2 patent drawing

AI summary

A method for performing a read of a flash memory includes storing configuration files for a plurality of RRD-compensating RNNs. A current number of PE cycles for a flash memory are identified and TVSO values are identified corresponding to the current number of PE cycles. A current retention time and a current number of read disturbs for the flash memory are identified. The configuration file of the RRD-compensating RNN corresponding to the current number of PE cycles, the current retention time and current number of read disturbs is selected and is loaded into a neural network engine to form an RNN core in the neural network engine. A neural network operation of the RNN core is performed to predict RRD-compensated TVSO values. The input to the neural network operation includes the identified TVSO values. A read of the flash memory is performed using the predicted RRD-compensated TVSO values.