Flash Memory Access Scheduling via Priority Preemption
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Solution Overview
Problem
Existing solutions for prioritizing memory access requests in multi-processor systems fail to efficiently manage performance inefficiencies and do not account for the priority of requests such as real-time execution, interrupts, or critical requests.
Innovation Solution
A system that includes memory access circuitry and processing circuitry, configured to receive read requests for instructions stored in non-volatile memory, determine the priority of the requests, preempt current access if necessary, and supply the instructions to the processing circuitry for execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple flash memory instances are used to handle read and write requests simultaneously, then access speed and throughput are improved, but system cost and device complexity increase
Solution Approach 1:
The patent implements dynamic request prioritization and preemption mechanisms that allow the single flash memory to adaptively handle different types of access requests (program, erase, read) based on their urgency and type. The memory access controller dynamically adjusts request handling priorities, enabling high-priority read requests to preempt lower-priority program/erase operations, thereby achieving efficient concurrent access patterns without requiring multiple physical memory instances.
2Device complexity
If a single flash memory is used to reduce cost and complexity, then device complexity is reduced, but access latency increases due to request prioritization overhead
Solution Approach 1:
The patent employs preliminary classification and prioritization of memory access requests at the controller level. Read requests are identified and flagged as high-priority before conflict occurs, enabling the system to proactively schedule and execute read operations before they would interfere with program or erase operations. This preliminary action minimizes latency by preventing conflicts rather than resolving them after they occur.
Solution Approach 2:
The memory access controller acts as an intermediary between processing cores and the single flash memory instance. It receives, prioritizes, and schedules all access requests, making intelligent decisions about which requests to grant access to the flash memory and when. This intermediary mechanism efficiently manages the single flash memory resource while minimizing access latency through smart request arbitration and preemption.
3Device complexity
If traditional prioritization mechanisms are used for single flash memory access, then device complexity is reduced, but performance efficiency deteriorates due to inability to handle multiple processor requests effectively
Solution Approach 1:
The patent segments the flash memory address space into distinct regions (e.g., code storage, data storage, configuration areas) and implements region-specific access policies. Different processing cores or software modules can be assigned to access specific regions, enabling parallel access patterns where multiple processors can simultaneously access different flash memory regions without conflict. This segmentation strategy maintains a single flash memory instance while achieving multi-processor throughput efficiency.
Data Source
AI summary
Various examples disclosed herein relate to trimming of system elements to prepare the elements for execution of boot code and application code. In an example embodiment, a system is provided. The system includes memory access circuitry and processing circuitry coupled to the memory access circuitry. The memory access circuitry is configured to receive a read request corresponding to a set of instructions for execution by processing circuitry stored in non-volatile memory, determine whether to preempt current access to the non-volatile memory corresponding to one or more access requests in favor of the read request based on a priority of the read request relative to the one or more access requests, obtain the set of instructions from the non-volatile memory, and supply the set of instructions to the processing circuitry. The processing circuitry executes the set of instructions.