Flash Memory Floating Gate Structure With Wider Process Window
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Solution Overview
Problem
The existing technology for forming flash memory devices has a small process window, leading to many defects and hindering device miniaturization and stability improvement.
Innovation Solution
A semiconductor structure is developed with a broadened process window, including a substrate, a floating gate dielectric layer, a word line structure, a floating gate with a sharp tip, a control gate dielectric layer, and a control gate. The method involves forming a mask structure, etching the floating gate and dielectric layer, and forming the word line structure, which reduces defects and allows for miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional flash memory device formation process is used, then device structure is formed, but process window is small resulting in many defects
Solution Approach 1:
The patent applies preliminary action by forming the floating gate with sharp tips before forming the control gate dielectric layer. This sequence ensures that the floating gate structure is established first, allowing subsequent layers to be formed around it with better control. The mask structure is removed to expose the floating gate, and then the control gate dielectric layer is formed, which broadens the process window and reduces defects compared to conventional approaches.
Solution Approach 2:
The patent changes the geometric parameters of the floating gate by forming sharp tips at both ends through selective etching. This parameter change (creating sharp tips instead of rounded or flat ends) improves the electric field distribution and enhances device performance. The sharp tip geometry is achieved by controlling the etching process to remove material from the floating gate ends, transforming the shape parameter to optimize device function.
2Volume of moving object
If device miniaturization is pursued, then storage capacity increases, but process window becomes smaller leading to more defects
Solution Approach 1:
The patent segments the formation process into distinct stages: first forming the floating gate dielectric layer and floating gate structure, then forming the control gate dielectric layer and control gate. This segmentation allows each layer to be optimized independently. The floating gate is formed with sharp tips through selective etching, and the control gate dielectric layer is formed subsequently, providing process flexibility that supports miniaturization while maintaining a reasonable process window.
Solution Approach 2:
The patent introduces dimensional changes by forming three-dimensional structures with sharp tips on the floating gate. The sharp tips create concentrated electric fields that enhance charge injection and storage efficiency. This dimensional feature (sharp tips extending vertically) allows for better control of electrical characteristics in miniaturized devices, compensating for the reduced scale and maintaining performance despite smaller dimensions.
3Ease of manufacture
If conventional formation process is used, then device is formed, but stability needs improvement
Solution Approach 1:
The patent applies self-service by allowing the floating gate structure to define its own geometry through selective etching. The mask structure is removed to expose the floating gate, and the etching process automatically creates sharp tips at the exposed ends. This self-organizing process reduces the need for additional alignment steps and improves device stability by ensuring consistent geometry formation. The process inherently creates the desired sharp-tip structure without requiring complex external control mechanisms.
Data Source
AI summary
A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes: providing a substrate; forming a plurality of initial memory cell structures on the substrate, and an initial memory cell structure including a floating gate dielectric layer disposed on the substrate, an initial floating gate disposed on the floating gate dielectric layer, a mask structure disposed on the initial floating gate, a control gate dielectric layer disposed on the initial floating gate and on sidewalls of the mask structure, and a control gate disposed on the control gate dielectric layer disposed on both sides of the mask structure; removing the mask structure to form an initial opening; etching the initial floating gate and the floating gate dielectric layer disposed at a bottom of the initial opening to form a word line opening; and forming a word line structure in the word line opening.