Flash Memory Processing Element With Capacitive Coupling

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Solution Overview

Problem

Conventional processors are inefficient for performing machine learning and machine learning-based inference due to the need for large numbers of iterative parallel computations, necessitating the development of specialized processors like neural or neuromorphic processors.

Innovation Solution

A processing element based on a flash memory cell is implemented, featuring a body with terminals connected to bit and source lines, a control gate, and a capacitive element between the charge storage element and the bit line, enhancing computational efficiency through improved linearity and operation range.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional processors are used for machine learning computations, then general-purpose computing is maintained, but computational efficiency and linearity for iterative parallel computations deteriorate

Engineering Contradiction:
Improvecomputational efficiencyVSAvoidlinearity for machine learning operations
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent changes the physical parameters of the memory cell by introducing a capacitive element coupled to the charge storage element, which modifies the electrical characteristics and linearity of the processing element to enable efficient machine learning computations

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The processing element is designed to perform multiple functions including storing data in the charge storage element and performing linear multiplication operations for machine learning, making it both a memory device and a computational unit

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If flash memory cell structure is used for processing elements, then non-volatile storage capability is achieved, but linearity and operation range for computational operations are limited

Engineering Contradiction:
Improvenon-volatile storage capabilityVSAvoidlinearity of computational operations
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The capacitive element acts as an intermediary component that couples to the charge storage element, mediating the electrical signals to improve linearity and operation range while preserving the non-volatile storage capability of the flash memory cell

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The addition of the capacitive element changes the electrical parameters of the processing element, specifically improving the linearity and expanding the operation range for computational operations while maintaining the flash memory's non-volatile characteristics

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enables efficient machine learning and inference operations by improving the linearity of processing elements, expanding their operation range and enhancing their ability to perform as linear multipliers, thus addressing the inefficiencies of conventional processors.

Implementation Method 1

a capacitive element between the charge storage element and the corresponding bit line

Methodology Applied
Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12073878B2Processing element and electronic device including processing element
Publication Date: 2024.08.27 SAMSUNG ELECTRONICS CO LTD
  • US12073878B2 patent drawing
  • US12073878B2 patent drawing
  • US12073878B2 patent drawing

AI summary

Disclosed is an electronic device which includes processing elements arranged in rows and columns, word lines connected with the rows of the processing elements, bit lines connected with the columns of the processing elements, body lines connected with the columns of the processing elements, and source lines connected with the rows of the processing elements. Each of the processing elements includes a first terminal connected with a corresponding bit line of the bit lines, a second terminal connected with a corresponding source line of the source lines, a control gate connected with a corresponding word line of the word lines, a floating gate between the control gate and a body, a body terminal connected with a corresponding body line of the body lines, and a capacitive element between the floating gate and the corresponding bit line.