Flash Memory Program Method Compensating High Temperature Stress
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Solution Overview
Problem
Flash memory systems face reduced read margins due to electric field coupling/F-poly coupling and high temperature stress, which widen threshold voltage distributions and make it difficult to secure a margin between states.
Innovation Solution
A program method for flash memory devices that involves primary and secondary programming operations to increase the read margin between adjacent states, where memory cells are programmed with multi-bit data and reprogrammed to have higher threshold voltages, specifically addressing the effects of high temperature stress and electric field coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the increment of program voltage is set to a small value to minutely control threshold voltage distributions, then the margin between states is secured, but the programming time increases
Solution Approach 1:
The patent applies preliminary action by performing a first programming operation to set threshold voltages to initial values, then performing a second programming operation to adjust them to final values. This two-stage approach allows for better control of threshold voltage distributions while managing programming time efficiently by preparing cells in advance and then making precise adjustments.
2Productivity
If electric field coupling occurs between adjacent memory cells during programming, then programming can proceed, but the threshold voltage distribution widens and read margin between states is reduced
Solution Approach 1:
The patent applies preliminary anti-action by performing a second programming operation after the first programming operation to counteract the threshold voltage shifts caused by electric field coupling. This compensatory programming adjusts the threshold voltages back to their intended values, preventing the widening of threshold voltage distributions and maintaining adequate read margins between states.
3Temperature
If high temperature stress causes charge drainage from floating gate to substrate, then threshold voltage decreases, but the read margin between states is reduced and state determination becomes difficult
Solution Approach 1:
The patent applies preliminary action by performing the first programming operation to set threshold voltages to initial values before the second programming operation. This preliminary programming establishes a baseline that can be adjusted later to compensate for high temperature stress effects, ensuring that state determination remains accurate even when threshold voltages shift due to temperature variations.
Solution Approach 2:
The patent applies feedback by performing a second programming operation that adjusts threshold voltages based on the effects observed from the first programming operation and high temperature stress. This compensatory adjustment uses feedback from the threshold voltage shifts to restore proper state separation, ensuring accurate state determination despite temperature-induced variations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively secures a sufficient read margin between states even when threshold voltages are affected by electric field coupling and high temperature stress, maintaining data integrity by ensuring accurate state determination.
Implementation Method 1
a voltage of floating gate FG of adjacent memory cell MCA rises due to a coupling between floating gates FG of the memory cells MCA and MCB. The rising threshold voltage is maintained due to a coupling between floating gates
Implementation Method 2
HTS means that charges accumulated in a floating gate of a memory cell are drained to a substrate. As the charges of the floating gate are reduced, threshold voltages of memory cells in respective states drop
Data Source
AI summary
A program method of a flash memory device having first and-second bitlines connected with a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The program method includes programming memory cells, connected to a selected row and first or second bitlines, with multi-bit data; and reprogramming programmed memory cells connected to a row disposed directly below the selected row and the first bitlines or the second bitlines, whereby increasing a read margin between adjacent states reduced due to high temperature stress (HTS).


