Flash Memory Program Disturb Mitigation via Localized Verify Levels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory systems face challenges in reducing program disturb, where unselected memory cells adjacent to the selected cell on a shared word line can be inadvertently programmed, leading to errors due to Gate Induced Drain Leakage (GIDL) and floating gate coupling effects.
Innovation Solution
Implementing a method that uses different verify levels and read compare values based on the position of the word line relative to a boosted region, allowing for targeted programming and reading to minimize the impact of program disturb by adjusting threshold voltage distributions and read thresholds.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If uniform verify levels are used for all word lines during programming, then the programming process is simple and fast, but program disturb occurs causing errors in unselected memory cells
Solution Approach 1:
The patent applies different verify levels to different word lines based on their position relative to the selected word line. Specifically, word lines adjacent to the selected word line use a first verify level, while other word lines use a second verify level. This local differentiation reduces program disturb in critical areas without unnecessarily complicating the entire programming process.
Solution Approach 2:
The patent changes the verify level parameter based on word line position. By adjusting the verify level threshold differently for adjacent versus non-adjacent word lines, the system optimizes programming reliability while managing complexity through selective parameter modification rather than complete process redesign.
2Reliability
If different verify levels are used for adjacent and non-adjacent word lines, then program disturb is reduced improving data integrity, but the programming process becomes more complex
Solution Approach 1:
The patent implements local quality by applying different verify levels specifically to word lines adjacent to the selected word line compared to other word lines. This targeted approach addresses the program disturb problem in the most critical areas (adjacent cells) without requiring complex differentiation across all word lines, thus maintaining ease of operation.
Solution Approach 2:
The patent segments the word lines into two groups: adjacent word lines and non-adjacent word lines. Each group receives an appropriate verify level, simplifying the control logic compared to treating each word line individually. This segmentation reduces operational complexity while still providing targeted protection against program disturb.
3Manufacturing precision
If higher verify levels are used for all word lines, then programming precision is improved, but program disturb increases causing more errors
Solution Approach 1:
The patent applies different verify levels to different word line positions: a first verify level for adjacent word lines and a second verify level for non-adjacent word lines. This local differentiation allows higher precision where needed (adjacent cells are more prone to program disturb) while using lower levels elsewhere, thus reducing overall program disturb while maintaining necessary precision.
Solution Approach 2:
The patent changes the verify level parameter based on spatial position relative to the selected word line. By lowering the verify level for non-adjacent word lines, the patent reduces the voltage stress and associated program disturb effects, while maintaining adequate precision for those less susceptible cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the effect of program disturb by shifting threshold voltage distributions to align with those of other memory cells, minimizing errors and maintaining data integrity.
Implementation Method 1
unselected memory cells adjacent to the selected cell on a shared word line can be inadvertently programmed, leading to errors due to Gate Induced Drain Leakage (GIDL)
Implementation Method 2
The threshold voltage of the transistor is controlled by the amount of charge that is retained on the floating gate
Data Source
Figure 1~2
Figure 3
Figure 4~5
AI summary
The unintentional programming of an unselected (or inhibited) non- volatile storage element during a program operation that intends to program another non-volatile storage element is referred to as "program disturb." A system is proposed for programming and/or reading non-volatile storage that reduces the effect of program disturb. In one embodiment, different verify levels are used for a particular word line (or other grouping of storage elements) during a programming process. In another embodiment, different compare levels are used for a particular word (or other grouping of storage elements) during a read process.