Flash Memory Program Method Peak Current Reduction
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Solution Overview
Problem
In NAND flash memory, the peak current during program operations is excessively high due to capacitive coupling between adjacent bit lines, leading to instability in internal supply voltages and operations of logic and other internal circuits.
Innovation Solution
A program method that switches the driving ability of the virtual voltage drive circuit from strong to weak during the program operation, specifically by charging selective and non-selective bit lines with a virtual voltage using a weak driving ability initially and then switching to a strong driving ability, and further limiting the drive current of pull-up transistors to reduce peak current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are distributed with narrow spacings to increase page capacity, then storage density is improved, but capacitive coupling between adjacent bit lines increases causing noise and interference
Solution Approach 1:
The patent divides the bit line selection into separate even and odd bit line selecting circuits, which operate at different times during readout operations. This temporal segmentation allows even and odd pages to be read alternately, effectively doubling the distribution spacing between active bit lines and reducing capacitive coupling noise while maintaining high page capacity
2Speed
If voltages are simultaneously applied to selective and non-selective bit lines during program operation, then programming speed is improved, but peak current increases causing supply voltage instability
Solution Approach 1:
The patent applies voltages to non-selective bit lines before applying voltages to selective bit lines during program operations. This preliminary action prepares the non-selective bit lines in advance, allowing subsequent selective bit line voltage application to proceed without causing excessive peak current, thus maintaining both programming speed and supply voltage stability
Solution Approach 2:
The patent employs staged voltage application to bit lines during program operations, where voltages are applied in sequences rather than simultaneously. This periodic action divides the voltage application process into distinct phases, controlling current peaks while maintaining programming efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the peak current during program operations, stabilizing internal and external supply voltages, thereby enhancing the reliability of logic and other internal circuits.
Implementation Method 1
the pull-up transistor P1 and the transistor HVNE are turned on and the pull-up transistor P2 and the pull-down transistor N1 are turned off by using a drive control circuit not shown during the time from t0 to t1. The external supply voltage EXVDD is provided to the output end as the virtual voltage VIRPWR via the pull-up transistor P1 with a weak driving ability
Implementation Method 2
the influence of capacitive coupling between the adjacent bit lines cannot be ignored. Therefore, one page is divided into 1/2 pages with an even page including even bit lines and an odd page including odd bit lines
Data Source
AI summary
A program method capable of reducing a peak current of a program operation is provided. The program method of a flash memory includes following steps: charging selective bit lines and non-selective bit lines by using a virtual voltage with weak driving ability during the time from t0 to t1 and a virtual voltage with strong driving ability during the time from t1 to t2, switching at least the non-selective bit lines to use the virtual voltage with weak driving ability for charging during at least the time from t2 to t3 when starting to discharge the selective bit lines connected to selective storage cells to a GND voltage level at time t2, and then applying program voltages to selective word lines.


