Flash Memory Program Time Reduction via Parallel Voltage Generation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory devices have long read and write cycles, which can be improved by using buffer memories to temporarily store data before transferring it to flash memory, but the total program time remains high due to significant data transfer and high voltage enable times.
Innovation Solution
A flash memory device and method that simultaneously generates a high voltage as a word line voltage and transfers data from a buffer memory to a page buffer circuit, allowing parallel operation of data transfer and high voltage setup, reducing the total program time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is transferred from buffer memory to page buffer circuit sequentially before high voltage generation, then data transfer completeness is ensured, but total program time increases
Solution Approach 1:
The patent initiates high voltage generation in advance before data transfer is complete. The high voltage generating circuit starts generating voltage while the data transfer operation is still in progress, rather than waiting for data transfer to finish first. This preliminary action reduces the total program time by overlapping the high voltage generation period with the data transfer period.
Solution Approach 2:
The patent maintains continuous useful action by overlapping two critical operations: data transfer from buffer memory to page buffer circuit, and high voltage generation for programming. Instead of sequential execution, both operations proceed simultaneously, maximizing resource utilization and reducing idle time in the programming process.
2Loss of time
If high voltage generation is performed before data transfer, then programming can start earlier, but data may not be ready causing programming errors
Solution Approach 1:
The patent employs a feedback mechanism where the page buffer circuit monitors data transfer status and provides feedback signals to the control logic. The control logic uses this feedback to determine when data transfer is complete and coordinates the timing of high voltage application accordingly, ensuring programming accuracy while minimizing delays.
Solution Approach 2:
The patent implements dynamic control of the programming process, where the timing and coordination of high voltage generation and data transfer are adaptively managed based on real-time status feedback. The system dynamically adjusts the sequencing and parallel execution of operations to optimize both speed and reliability.
3Device complexity
If sequential programming operations are used, then process control is simplified, but programming speed decreases
Solution Approach 1:
The patent segments the programming process into independent controllable modules: data transfer operation, high voltage generation operation, and programming operation. Each module can be controlled and timed independently, allowing parallel execution while maintaining manageable control complexity through modular design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the total program time by performing high voltage generation during data transfer, optimizing the time required for programming operations in flash memory devices.
Implementation Method 1
As well known in the art, the memory cells forming a NAND flash memory may be erased and/or programmed using a phenomenon called Fowler-Nordheim tunneling current
Data Source
AI summary
Disclosed is a program method for a flash memory device which includes; storing data in a buffer memory and generating a high voltage as a word line voltage. When transmission of data to the buffer memory is complete, the program method simultaneously transfers data in the buffer memory to a page buffer circuit, and programs data in the page buffer circuit in a memory cell array according to the word line voltage.