Flash Memory Program-Verify Process with Dynamic PPV Bucket Size

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Solution Overview

Problem

The existing program-verify process for flash memory cells is inefficient due to the constant size of the pre-program verify (PPV) bucket, which leads to increased programming time, especially for the weakest cells.

Innovation Solution

Optimizing the size of the PPV bucket by maintaining a larger size until a sufficient number of cells are fully programmed, and then reducing it to minimize programming time without compromising distribution narrowing.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If the PPV bucket size is kept constant throughout the program-verify process, then the charge distribution remains manageable, but the programming time increases significantly due to repeated iterations for weakest cells

Engineering Contradiction:
Improvecharge distribution precisionVSAvoidprogramming time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The patent applies dynamics by making the PPV bucket size adjustable rather than fixed. The bucket size is dynamically reduced when a sufficient number of cells (threshold, e.g., 90%) are fully programmed, allowing the system to adapt to different stages of programming and optimize performance at each stage.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of PPV bucket size based on programming progress. When the number of fully programmed cells reaches a threshold, the bucket size is reduced to a smaller value, thereby modifying the programming characteristics to reduce overall programming time while maintaining precision.

Inventive Principle:
Principle #35Parameter changes

2Loss of time

If the PPV bucket size is reduced early in the program-verify process, then programming time is minimized, but the charge distribution becomes wider and programming precision deteriorates

Engineering Contradiction:
Improveprogramming timeVSAvoidcharge distribution precision
Core Design Contradiction:
Loss of timeVSManufacturing precision

Solution Approach 1:

The patent applies preliminary action by maintaining a larger PPV bucket size during the initial stages of programming when charge distribution is still forming. This preliminary large bucket size ensures that charge distribution remains narrow and precise before the system transitions to a smaller bucket size for final optimization.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts the bucket size based on the number of fully programmed cells. The transition from large to small bucket size occurs only when a sufficient proportion of cells are fully programmed, ensuring that precision is maintained during the critical formation phase before time optimization begins.

Inventive Principle:
Principle #15Dynamics

3Productivity

If a threshold-based dynamic adjustment of PPV bucket size is implemented, then programming efficiency is optimized, but the control complexity increases

Engineering Contradiction:
Improveprogramming efficiencyVSAvoidcontrol complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements feedback by continuously monitoring the number of fully programmed cells and using this information to determine when to reduce the PPV bucket size. This feedback mechanism ensures that the bucket size adjustment is based on actual programming progress, optimizing efficiency while maintaining manageable control through a simple threshold-based decision.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12322455B2Program verify process having placement aware pre-program verify (PPV) bucket size modulation
Publication Date: 2025.06.03 INTEL NDTM US LLC
  • US12322455B2 patent drawing
  • US12322455B2 patent drawing
  • US12322455B2 patent drawing

AI summary

An apparatus is described. An apparatus includes controller logic circuitry to perform a program-verify programming process to a flash memory chip. The program-verify programming process is to reduce a size of a pre-program verify (PPV) bucket in response to a number of cells being fully programmed to a same digital state. The number of cells are less than a total number of cells to be programmed to the same digital state.