Flash Memory Programming Algorithm Adapted to Device Age
Solution Overview
Problem
Current non-volatile memory devices face challenges in achieving high capacity and performance due to noise in programming operations and the need for precise data storage as devices scale down, leading to issues with oxide interface trapping and programming/erase saturation.
Innovation Solution
The solution involves a method of operating non-volatile memory devices using alternating pulse and verify operations, where voltage levels for selected memory cells are adjusted based on age indications, and voltage waveforms are individually characterized and trimmed for each memory chip to account for variations in device characteristics across different age ranges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional programming algorithms are used for high-density flash memory, then manufacturing cost is reduced, but programming precision deteriorates due to noise and oxide interface trapping
Solution Approach 1:
The patent implements dynamic programming algorithms that adapt to the age of memory blocks. The algorithm selects different programming strategies based on block age (fresh vs. worn blocks), adjusting pulse widths, voltage levels, and verify operations dynamically. This resolves the contradiction by making the system flexible rather than static, improving precision without requiring a completely new algorithm for all cases.
Solution Approach 2:
The patent changes multiple programming parameters including pulse width, voltage level, and number of verify operations based on block age. For fresh blocks, shorter pulses and fewer verifies are used, while worn blocks receive extended pulses and additional verifies. This parameter adaptation improves programming precision across the entire memory array without uniformly increasing complexity.
2Reliability
If multi-state memory cells are used to increase capacity, then storage density is improved, but reliability deteriorates due to noise in reading and programming
Solution Approach 1:
The patent implements multiple verify operations within the programming sequence, where the threshold voltage of each cell is measured after each programming pulse and the result feeds back to adjust subsequent programming pulses. This feedback mechanism ensures accurate placement of threshold voltages in multi-state cells, improving reliability while maintaining high storage capacity.
Solution Approach 2:
The patent performs preliminary characterizations of memory chips and pre-determines optimal programming parameters for different age ranges before actual programming operations. This preliminary action allows the system to prepare appropriate programming sequences in advance, reducing noise and improving reliability during actual data storage operations.
3Productivity
If fixed programming parameters are used for all memory blocks, then device complexity is reduced, but programming performance deteriorates due to variations in device characteristics across age ranges
Solution Approach 1:
The patent introduces dynamic control logic that automatically adjusts programming parameters based on block age. The control circuit determines whether a block is fresh or worn and selects appropriate programming sequences accordingly. This dynamic approach improves productivity by optimizing parameters for each block's specific characteristics without requiring manual intervention or overly complex user-side control.
Solution Approach 2:
The patent segments the memory array into fresh and worn blocks based on age indications, and applies different programming algorithms to each segment. This segmentation allows the system to optimize programming performance for each block type independently, improving overall productivity while keeping the control logic manageable through clear separation of handling strategies.
4Manufacturing precision
If higher voltage levels are applied during programming to overcome noise, then programming speed is improved, but manufacturing precision deteriorates due to oxide interface trapping and saturation
Solution Approach 1:
The patent uses periodic programming pulses with varying widths and voltages rather than continuous high-voltage application. Multiple short pulses with increasing width and voltage are applied in sequence, allowing the oxide interface to stabilize between pulses. This periodic action achieves precise threshold voltage programming while maintaining reasonable programming speed through efficient pulse sequencing.
Solution Approach 2:
The patent dynamically changes programming parameters including pulse width and voltage level based on block age and programming stage. For fresh blocks, shorter lower-voltage pulses are used; for worn blocks, longer higher-voltage pulses are applied. This parameter adaptation maintains manufacturing precision across all block ages while optimizing programming speed for each specific condition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming performance and endurance by adapting programming parameters to the age of the memory device, reducing noise and improving writing accuracy, thereby increasing the memory device's capacity and reliability.
Implementation Method 1
The threshold voltage characteristic of the transistor is controlled by the amount of charge that is retained on the floating gate
Implementation Method 2
In 'hot electron injection,' a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric onto the floating gate
Implementation Method 3
In 'tunneling injection,' a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate
Implementation Method 4
For EEPROM, a memory cell is electrically erasable, by applying a high voltage to the substrate relative to the control gate so as to induce electrons in the floating gate to tunnel through a thin oxide to the substrate channel region
Data Source
AI summary
In a non-volatile memory device, the parameters used in write and erase operation are varied based upon device age. For example, in a programming operation using a staircase waveform, the amplitude of the initial pulse can be adjusted based upon the number of erase-program cycles (hot count) of the block containing the selected physical page for the write. This arrangement can preserve performance for relatively fresh devices, while extending life as a devices ages by using gentler waveforms as the device ages.