Flash Memory Programming with Parallel Bitscan and Predictive Verification
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Solution Overview
Problem
Conventional flash memory programming methods are inefficient due to the need for repeated bitscan, program, and verify steps, which can prolong programming time and increase error rates, especially in multi-level cell configurations where the margin for error is smaller.
Innovation Solution
The method involves applying programming pulses and verifying memory cells in parallel with bitscan operations, allowing for predictive completion of programming cycles without subsequent verification, and applying additional programming voltages to ensure error correction within Error Correction Code (ECC) capacity, thereby optimizing programming speed and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If repeated bitscan, program, and verify steps are performed sequentially, then programming accuracy is improved, but programming time increases
Solution Approach 1:
The patent performs bitscan operations in advance during parallel programming steps rather than waiting for sequential completion. By predicting which cells will reach target levels based on previous observation and performing bitscan提前, the method eliminates waiting time while maintaining verification accuracy through subsequent confirmatory bitscan operations.
Solution Approach 2:
The patent eliminates idle waiting time by continuously performing useful operations. While programming pulses are being applied to memory cells, bitscan operations are simultaneously performed on other cells or in parallel channels. This continuous utilization of processing resources maintains programming accuracy through thorough verification while maximizing throughput by eliminating sequential bottlenecks.
2Reliability
If more verification steps are performed, then error detection is improved, but programming complexity increases
Solution Approach 1:
The patent performs preliminary bitscan operations to identify cells approaching target levels before final verification. This early identification allows the system to focus subsequent verification resources on critical cells, maintaining high error detection capability while reducing the overall number of verification steps needed compared to universal repeated verification of all cells.
Solution Approach 2:
The patent employs error detection and correction codes (ECC) that automatically verify and correct programming errors without requiring complex external verification circuitry. The ECC mechanism provides self-verification capability within the memory system, improving error detection while minimizing additional programming complexity by using standardized error correction algorithms.
3Productivity
If programming is completed without subsequent verification, then programming speed is improved, but data reliability decreases
Solution Approach 1:
The patent performs preliminary verification through bitscan operations during the programming process itself, identifying cells that have reached target levels before the programming cycle formally concludes. This advance verification allows the system to confidently complete programming without time-consuming post-programming verification steps, maintaining both high speed and reliability through predictive verification.
Solution Approach 2:
The patent implements continuous feedback through bitscan operations that monitor programming progress in real-time. This feedback mechanism provides information about which cells have reached target levels, allowing the system to dynamically adjust programming termination decisions. The feedback ensures data reliability by confirming proper programming before completion while enabling speed improvements by avoiding unnecessary verification of already-programmed cells.
4Reliability
If additional programming voltages are applied to ensure ECC capacity, then data reliability is improved, but energy consumption increases
Solution Approach 1:
The patent applies additional programming voltages selectively to only those memory cells that require them to reach target levels and satisfy ECC requirements, rather than applying high voltages uniformly to all cells. This localized application of enhanced programming voltage ensures data reliability for critical cells while minimizing energy consumption by avoiding unnecessary high-voltage application to already-sufficient cells.
Solution Approach 2:
The patent dynamically adjusts programming voltage parameters based on real-time feedback from bitscan operations and ECC status. When cells approach target levels but require additional programming to meet ECC capacity requirements, the system modifies voltage parameters to provide the necessary additional programming. This parameter adaptation ensures data reliability while optimizing energy consumption by applying additional voltage only when and where needed rather than using fixed high-voltage programming throughout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces programming time by hiding the bitscan process within programming steps and ensures that memory cells reach target levels within ECC correction capacity, enhancing data reliability and storage efficiency in flash memory systems.
Implementation Method 1
In 'hot electron injection,' a high voltage applied to the drain accelerates electrons across the substrate channel region. At the same time a high voltage applied to the control gate pulls the hot electrons through a thin gate dielectric onto the floating gate.
Implementation Method 2
In 'tunneling injection,' a high voltage is applied to the control gate relative to the substrate. In this way, electrons are pulled from the substrate to the intervening floating gate.
Data Source
AI summary
In a programming operation that includes repeated bitscan, program, and verify steps, the bitscan steps may be hidden by performing bitscan in parallel with program preparation and program steps. The effect of a program step may be predicted from previous observation so that when a bitscan indicates that the memory cells are close to being programmed, a last programming step may be completed without subsequent verification or bitscan steps.