Flash Memory Programming Column Segmentation and Voltage Control
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Solution Overview
Problem
Conventional flash memory devices face challenges in programming speed, with long programming times making them unsuitable for re-writable data storage applications, and are prone to read and write errors due to disturbances in neighboring cells, especially in dual bit architectures.
Innovation Solution
A method for fast programming of flash memory arrays by starting with cells in the 'off' state and programming column by column, using lower threshold voltage to achieve '01', '10', and '11' states, with concurrent voltage application to selected cells and floating voltages for unselected cells to minimize disturbance, and incorporating a program verify operation to ensure accurate programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional flash memory programming method is used, then cells can be programmed, but programming time is long (making them unsuitable for re-writable data storage applications)
Solution Approach 1:
The patent segments the flash memory array into column pages and programs them sequentially column by column. Each column page is programmed independently using a column page program operation, which allows parallel programming within each column while maintaining control over the programming process. This segmentation enables faster programming by reducing the time needed to program the entire array compared to conventional row-by-row programming methods.
Solution Approach 2:
The patent changes the programming parameters by using lower threshold voltage to achieve programming in the off state, rather than the conventional approach. The programming operation applies a first voltage to select column pages and a second voltage to program the cells, with the second voltage being lower than conventional programming voltages. This parameter change reduces programming time while maintaining programming reliability.
2Quantity of substance
If dual bit architecture is used to increase storage density, then more data can be stored, but read and write errors increase due to disturbances in neighboring cells
Solution Approach 1:
The patent applies local quality by programming column pages independently and applying different voltage levels to selected and unselected cells. Unselected cells in the same column page receive a floating voltage that prevents disturbance, while selected cells receive the programming voltage. This localized voltage application minimizes cross-talk and disturbance between neighboring cells, reducing read and write errors in dual bit architectures.
Solution Approach 2:
The patent inverts the conventional programming approach by programming in the off state using lower threshold voltage, rather than programming in the on state with higher threshold voltage. This inversion reduces the disturbance effect on neighboring cells and minimizes read and write errors, while still achieving the required storage density through dual bit architecture.
3Reliability
If high voltage is applied to program cells to ensure reliable programming, then programming is reliable, but programming time increases
Solution Approach 1:
The patent changes the programming voltage parameter by using a lower second voltage for programming cells in the off state, rather than applying high voltage. This voltage reduction decreases the programming time while maintaining programming reliability through the column page programming approach and proper voltage sequencing. The first voltage selects column pages and the lower second voltage programs the cells without requiring excessive time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases programming speed, allowing 20 k-200 k bits to be programmed at once in 1 msec, reduces disturbance effects, and maintains efficient read speeds, making it suitable for applications like digital cameras without requiring new fabrication processes.
Implementation Method 1
programming consists of lowering the threshold voltage on the selected cells
Implementation Method 2
concurrent voltage application to selected cells and floating voltages for unselected cells to minimize disturbance
Data Source
AI summary
Embodiments of the present invention disclose a method of utilizing a flash memory array to decrease programming time while maintaining sufficient read speeds. An array of cells is programmed and read in pages that are oriented in the column direction, parallel to the bit lines in the array. An erased cell in the present invention is a cell in the “off” state. According to the present invention a cell is programmed by lowering the threshold voltage of the cell, thereby turning the cell “on.” An array of cells is programmed read in a sector-by-sector method, wherein a sector consists of units situated diagonally adjacent to each other, and a unit consists of multiple parallel column-oriented pages.