Flash Memory Programming Controller with Dedicated Acceleration Hardware
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Solution Overview
Problem
Flash memory devices, particularly NAND flash devices, face performance limitations in data programming due to their serial access nature, which restricts random access capabilities and increases processing time and resource consumption in current systems.
Innovation Solution
A method and apparatus that divide the data programming process into three stages - front-end, mid-end, and back-end processing - utilizing a routing engine and an accelerator to manage data flow through dedicated hardware, reducing processor loading and optimizing data programming by activating specific stages based on operation settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND flash devices are used for data storage, then storage capacity and density are improved, but random access capability deteriorates and serial access time increases
Solution Approach 1:
The patent segments the data programming process into three distinct stages: front-end processing (data reception and initial preparation), mid-end processing (encryption and parity generation), and back-end processing (actual flash programming). This segmentation allows each stage to be optimized independently and processed in parallel where possible, mitigating the serial access limitation of NAND flash while maintaining high storage capacity.
Solution Approach 2:
The patent performs preliminary actions by preparing data in the front-end stage (reception, buffering, and preprocessing) before actual flash programming begins. The mid-end stage performs encryption and parity generation in advance of the back-end programming operation. This preliminary preparation reduces the critical path time during the actual programming phase, improving effective access speed without sacrificing storage capacity.
2Device complexity
If traditional flash programming methods are used, then device simplicity is maintained, but processor loading increases and programming performance deteriorates
Solution Approach 1:
The patent introduces a dedicated flash controller as an intermediary between the host processor and flash memory devices. This controller includes specialized hardware components (front-end engine, mid-end engine with RAID functionality, back-end engine) that handle the complex programming operations. The host processor only needs to issue simple commands, dramatically reducing processor loading while significantly improving programming performance through hardware-accelerated parallel processing.
Solution Approach 2:
The patent replaces software-based processing with hardware-based processing for critical path operations. The front-end, mid-end, and back-end engines are implemented as dedicated hardware circuits that perform data reception, encryption/parity generation, and flash programming respectively. This mechanical substitution eliminates software overhead and enables simultaneous execution of multiple operations, improving productivity without substantially increasing perceived system complexity.
3Reliability
If all processing stages are activated for every data programming transaction, then data security and reliability are improved, but processing time and resource consumption increase
Solution Approach 1:
The patent implements dynamic stage activation where the front-end, mid-end, and back-end processing stages can be selectively activated or deactivated based on the specific programming transaction requirements. The controller receives operation settings that indicate which stages should be activated, allowing the system to adapt to different security and performance needs. For example, trusted applications may skip encryption (mid-end), while security-sensitive data triggers all stages, optimizing the balance between reliability and processing time on a per-transaction basis.
Data Source
AI summary
The invention relates to a method, and an apparatus for programming data into flash memory. The method includes: driving, by the routing engine, a host interface (I/F) according to the front-end parameter set when determining that a front-end processing stage needs to be activated for the data-programming transaction; driving, by the accelerator, a Redundant Array of Independent Disks (RAID) engine according to the mid-end parameter set when receiving an activation message of the data-programming transaction from the routing engine and determining that a mid-end processing stage needs to be activated; and driving, by the accelerator, a data access engine according to the back-end parameter set when determining that the mid-end processing stage for the data-write transaction does not need to be activated or the mid-end processing stage for the data-write transaction has been completed, and a back-end processing stage for the data-write transaction needs to be activated.