Flash Memory Programming via Dedicated RAID and Data Access Engines

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Solution Overview

Problem

Existing flash memory programming methods are inefficient, leading to high processor loading and computing resource consumption, particularly due to the serial access nature of NAND flash devices and the need for extensive firmware operations.

Innovation Solution

The proposed solution involves a method and apparatus that utilize dedicated hardware circuits and a controller to read operating settings from SRAM, manage RAID engines for mid-end processing, and direct data access engines for back-end processing, thereby optimizing data programming in flash memory.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If firmware operations are used for data programming in flash memory, then data programming can be performed, but processor loading and computing resource consumption increase

Engineering Contradiction:
Improvedata programming performanceVSAvoidprocessor loading and computing resource consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data programming process into multiple independent hardware modules: a controller for managing operations, a RAID engine for mid-end processing (encryption/encoding), and a data access engine for back-end processing. Each module operates independently with dedicated hardware circuits, eliminating the need for firmware operations and reducing processor loading while maintaining data programming functionality.

Inventive Principle:
Principle #1Segmentation

2Productivity

If NAND flash serial access method is used, then data can be programmed into flash memory, but data programming performance is limited

Engineering Contradiction:
Improvedata programming performanceVSAvoiddata programming speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

The patent replaces the software-based firmware control mechanism with dedicated hardware circuits. The controller, RAID engine, and data access engine are all implemented as hardware components that operate in parallel, substituting the sequential firmware operation model with concurrent hardware processing, thereby overcoming the speed limitations of serial access methods.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If firmware operations are performed for each data programming task, then data can be programmed, but system performance deteriorates

Engineering Contradiction:
Improveoverall system performanceVSAvoidfirmware operation complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent implements self-service through automated hardware-based processing. The controller automatically manages data flow between the RAID engine and data access engine, with each module performing its designated function (encryption/encoding, programming) without requiring firmware intervention. This hardware-level automation reduces system complexity and improves overall performance by eliminating the overhead of firmware operations for each data programming task.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12223199B2Method and apparatus for programming data arranged to undergo specific stages into flash memory based on virtual carriers
Publication Date: 2025.02.11 SILICON MOTION INC
  • US12223199B2 patent drawing
  • US12223199B2 patent drawing
  • US12223199B2 patent drawing

AI summary

The invention relates to a method, and an apparatus for programming data into flash memory. The method includes: reading operating settings of a virtual carrier; setting a redundant array of independent disks (RAID) engine for driving the RAID engine to complete a designated encryption or encoding operation on first data associated with the virtual carrier when the operation settings indicate that the first data associated with the virtual carrier need to go through a mid-end processing stage; and sending a programming index to a data access engine for driving the data access engine to read a programming table from the SRAM, and program the second data associated with the virtual carrier into a designated address in a flash module when the operation settings indicate that the second data associated with the virtual carrier need to go through the back-end processing stage.