Multi-Level Flash Memory Programming via Lowest-Charge State Transition
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Solution Overview
Problem
Existing methods for programming multilevel flash memory cells face latency issues and error conditions due to the physical limitations of floating gate flash memory, where state transitions from higher to lower charge states are not permitted, leading to invalid state transitions and delayed data writing.
Innovation Solution
The method involves programming bits in an order of significance by transitioning the multilevel storage device to the lowest-charge state where the programmed bits have their correct values, allowing subsequent bits to be programmed without prohibited state changes, even if initial bits not yet programmed have incorrect values, thus avoiding invalid transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the cell is programmed to preserve all previously programmed bit positions, then reliability is improved, but latency increases because all data must arrive before programming can begin
Solution Approach 1:
The patent applies partial action by programming only the bits that have arrived so far, rather than waiting for all bits. The cell is programmed to the lowest-charge state consistent with the currently available data, accepting that some bits may be temporarily incorrect but will be corrected when remaining data arrives. This resolves the contradiction by sacrificing perfect accuracy temporarily to eliminate latency.
2Manufacturing precision
If data writing waits for all bit positions to arrive, then manufacturing precision is improved, but productivity deteriorates due to latency
Solution Approach 1:
The patent applies preliminary action by performing programming operations on the bits that are currently available, rather than waiting for all data to arrive. The system preliminarily programs the cell to a state consistent with available data, and will later adjust the state when remaining data arrives. This enables overlapping of data arrival and programming operations, improving productivity while maintaining eventual accuracy.
3Reliability
If encoding states are remapped to avoid invalid transitions, then reliability is improved, but latency increases because all pages must arrive
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the charge state parameter of the memory cell during the programming process. Instead of using a fixed encoding scheme, the system changes the charge state to the lowest-charge state consistent with currently available data for each bit position. This dynamic parameter adjustment allows progressive programming without waiting for all data, resolving the contradiction between reliability and latency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces latency by allowing flexible programming sequences and partial data writing without error conditions, enabling efficient storage in multilevel flash memory devices by ensuring all bits have correct values by the end of the programming process.
Implementation Method 1
A memory cell may be programmed by inserting electrons onto the floating gate (e.g., via channel hot-electron programming or Fowler-Nordheim tunneling)
Implementation Method 2
A memory cell may be programmed by inserting electrons onto the floating gate (e.g., via channel hot-electron programming or Fowler-Nordheim tunneling)
Data Source
AI summary
In a multi-level memory cell, when data to be programmed arrives, the cell is programmed to the lowest-charge state in which any bit position that is being programmed or has already been programmed has the correct value, regardless of the value in that state of any bit position that has not yet been programmed and is not being programmed. The programming of other bit positions based on subsequently arriving data should not then require a transition to an impermissible lower energy state. Although this may result in a transient condition in which some bits have the wrong value, by the time programming is complete, all bits would be expected to have the correct value. A cell may contain any number of bits equal to or greater than two, and programming may be performed cyclically (e.g., from LSB to MSB), anticyclically (e.g., from MSB to LSB), or in any random order.