Flash Memory Programming Order for Floating Gate Coupling
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Solution Overview
Problem
Non-volatile memory devices face programming errors due to cross coupling between adjacent memory cells, where higher-programmed cells adversely affect their neighbors, leading to unwanted changes in programming states.
Innovation Solution
A programming technique where memory cells are programmed in descending order of their programming values, with cells requiring higher programming values being programmed first, and those requiring lower values second, to minimize adverse incremental programming effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are programmed sequentially in row-by-row order, then programming operation can be completed, but cross coupling between adjacent floating gates causes programming errors
Solution Approach 1:
The patent applies preliminary action by sorting incoming data in descending order of programming values before programming operations. This reordering ensures that cells requiring higher programming values (which have greater potential to cause cross-coupling errors) are programmed first, before adjacent cells are programmed. This preliminary sorting action prevents the cross-coupling problem from occurring in the first place, rather than attempting to correct it afterward.
2Area of stationary object
If adjacent memory cells are programmed in sequence, then programming coverage is achieved, but higher-programmed cells adversely affect neighboring cells through floating gate coupling
Solution Approach 1:
The patent applies inversion by reversing the conventional programming order. Instead of programming cells in arbitrary or ascending order, the system programs cells in descending order of their target programming values. This inversion ensures that cells with higher programming values (which create stronger electric fields and greater cross-coupling effects) are programmed first, before their neighbors are programmed. This reverses the typical sequence that causes problems and eliminates the harmful cross-coupling effects.
3Quantity of substance
If memory cells are programmed to higher programming values, then data storage capacity is improved, but the magnitude of adverse incremental programming increases
Solution Approach 1:
The patent applies preliminary action by pre-sorting the programming sequence based on target programming values before execution. By identifying and programming high-value cells first (before they can cause adverse incremental programming to neighbors), the system eliminates the harmful effect at its source. This preliminary ordering action allows the system to program cells to higher programming values (increasing storage capacity) without suffering from the cross-coupling problems that would otherwise occur.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This technique reduces the occurrence and magnitude of programming errors by ensuring that cells already programmed are less affected by subsequent programming operations, thereby improving the accuracy of programming in memory cell arrays.
Implementation Method 1
program the memory cell (by injecting electrons onto the floating gate)
Implementation Method 2
non-volatile memory cells include a floating gate
Implementation Method 3
Various combinations of voltages are applied to the control gate, source and drain to program the memory cell
Implementation Method 4
program the memory cell (by injecting electrons onto the floating gate), to erase the memory cell (by removing electrons from the floating gate)
Data Source
AI summary
An improved programming technique for non-volatile memory cell arrays, in which memory cells to be programmed with higher programming values are programmed first, and memory cells to be programmed with lower programming values are programmed second. The technique reduces or eliminates the number of previously programmed cells from being adversely incrementally programmed by an adjacent cell being programmed to higher program levels, and reduces the magnitude of adverse incremental programming for most of the memory cells, which is caused by floating gate to floating gate coupling. The memory device includes an array of non-volatile memory cells and a controller configured to identify programming values associated with incoming data, and perform a programming operation in which the incoming data is programmed into at least some of the non-volatile memory cells in a timing order of descending value of the programming values.