Flash Memory Programming Sequence for Interference Control
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Solution Overview
Problem
In multiple level NAND flash memory cells, tight threshold voltage distribution is challenging due to floating gate-to-floating gate capacitance interference, which can cause variations in programmed threshold voltages, leading to data corruption or loss, especially as cells become miniaturized and programming states become more precise.
Innovation Solution
A programming sequence is implemented that separates programming operations for adjacent logical memory pages by intervening operations on other memory cells, using erase compaction to maintain tight threshold voltage distributions and reduce interference, while allowing for progressive programming of memory cells to achieve precise voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are miniaturized to increase density, then storage capacity is improved, but floating gate-to-floating gate capacitance interference increases causing threshold voltage variations
Solution Approach 1:
The patent segments the programming process into multiple sequential programming pulses applied to different word lines in a specific sequence. By dividing the programming operations and executing them in a predetermined sequence, the patent reduces simultaneous interference between adjacent floating gates while still achieving the desired threshold voltage distribution for miniaturized cells.
2Productivity
If programming operations are performed on adjacent logical memory pages simultaneously, then programming speed is improved, but program disturb and threshold voltage variations increase
Solution Approach 1:
The patent implements periodic action by applying programming pulses in a sequential pattern across different word lines rather than simultaneously. The predetermined sequence creates periodic programming intervals that allow interference to subside between pulses, reducing program disturb while maintaining acceptable programming throughput through efficient sequencing.
3Reliability
If tight threshold voltage distribution is enforced to prevent data corruption, then data reliability is improved, but programming precision requirements increase
Solution Approach 1:
The patent employs feedback mechanisms through verification operations that read back the programmed threshold voltages after each programming pulse. Based on the verification results, the programming process is adjusted by applying additional pulses only where needed, allowing tight threshold voltage distribution to be achieved while compensating for variations in programming precision through iterative correction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the negative effects of program disturb and floating gate-to-floating gate interference, ensuring accurate data storage and retrieval by maintaining tight threshold voltage distributions, reducing data corruption, and improving programming speed and reliability.
Implementation Method 1
floating gate-to-floating gate capacitance interference, which can cause variations in programmed threshold voltages
Data Source
AI summary
Methods, apparatus, systems, and data structures are disclosed, including a plurality of multiple level memory cells, each of the plurality of multiple level memory cells coupled to one of a plurality of wordlines and each of the plurality of multiple level memory cells including a plurality of logical memory pages; a control circuit coupled to the plurality of wordlines, the control circuit operable to progressively program each of the plurality of multiple level memory cells in at least one sequence including separation of the programming of a first logical memory page and a second logical memory page in any one of the plurality of multiple level memory cells by at least N−1 programming operations to memory cells either coupled to a different wordline or included in a different logical even page or a different logical odd page.