Flash Memory Programming Threshold Voltage Imbalance
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Solution Overview
Problem
The existing programming methods for flash memory devices suffer from threshold voltage imbalance due to interference effects, particularly in multi-level cell (MLC) flash memory devices, which deteriorates program characteristics and reduces sensing margin.
Innovation Solution
The method involves using incremental step pulse programming (ISPP) with specific voltage adjustments, where a second verifying voltage is applied to even bit lines, smaller than the first verifying voltage for odd bit lines, to mitigate interference effects and achieve a normal threshold voltage distribution, ensuring that memory cells on both types of bit lines have similar distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional programming method is used for MLC flash memory, then the programming speed is maintained, but threshold voltage imbalance occurs due to interference effects between adjacent memory cells
Solution Approach 1:
The patent applies different verifying voltages to even and odd bit lines. Specifically, a first verifying voltage is applied to odd bit lines and a second verifying voltage is applied to even bit lines during the programming process. This local differentiation compensates for the interference effects that occur between adjacent memory cells, ensuring that threshold voltage distribution remains uniform across all cells despite the interference from neighboring cells being programmed.
2Productivity
If memory cells are programmed sequentially on adjacent bit lines, then the programming operation can be completed, but the sensing margin is reduced due to threshold voltage shift
Solution Approach 1:
The patent applies a preliminary compensating voltage to the even bit line before programming the adjacent odd bit line. By applying the second verifying voltage to the even bit line in advance, the interference effect from the subsequent odd bit line programming is counteracted. This preliminary anti-action prevents the threshold voltage shift that would otherwise reduce the sensing margin, allowing sequential programming to proceed without compromising reliability.
3Device complexity
If the same verifying voltage is applied to all bit lines, then the programming process is simple, but threshold voltage distribution becomes uneven due to interference effects
Solution Approach 1:
The patent implements a dual verifying voltage scheme where odd bit lines receive a first verifying voltage and even bit lines receive a second verifying voltage. This local quality differentiation addresses the interference effects specific to each bit line position, ensuring uniform threshold voltage distribution across all memory cells while maintaining manageable process complexity through systematic voltage application.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces threshold voltage imbalance, improving program characteristics and maintaining a stable threshold voltage distribution, thereby enhancing the performance of MLC flash memory devices by ensuring consistent programming across both even and odd bit lines.
Implementation Method 1
one of the causes for the change is an interference effect due to capacitance between cells
Data Source
AI summary
A method of programming in a flash memory device is disclosed. The method includes programming a first memory cell coupled to an even bit line by applying a first program voltage to a word line, verifying whether or not the first memory cell is programmed through a first verifying voltage, and programming the first memory cell using a program voltage increased in sequence by a step voltage than the first program voltage in case that the first memory cell is not programmed programming a second memory cell coupled to an odd bit line by applying the first program voltage to the word line, and verifying whether or not the second memory cell is programmed through a second verifying voltage higher than the first verifying voltage, and programming the second memory cell using a program voltage increased in sequence by the step voltage than the first program voltage in case that the second memory cell is not programmed.