Flash Memory Programming Verification Optimization
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Solution Overview
Problem
Existing flash memory technologies face inefficiencies in programming operations due to the high number of verify operations required, which increases programming time and reduces performance.
Innovation Solution
The proposed method involves dividing memory cells into target groups based on their program states and using a verify voltage specific to each group. After the second memory cell in a target group passes verification, it undergoes additional program operations without further verification, reducing the total number of verifications needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If verify operations are performed on all memory cells after each program operation, then programming precision is improved, but programming time increases
Solution Approach 1:
The patent applies local quality by differentiating verification strategies for different memory cells based on their target program states. Memory cells are divided into target groups where cells with the same target program state receive verification, while cells with different target states receive different verification treatments. This localized differentiation reduces unnecessary verifications while maintaining required precision for critical cells.
Solution Approach 2:
The patent segments memory cells into multiple target groups based on their target program states. Each group is verified using a dedicated verify voltage corresponding to that group's target state. This segmentation allows parallel verification processing and eliminates redundant verifications across different cell types, reducing overall verification time while maintaining precision.
2Reliability
If multiple verify operations are performed to ensure programming accuracy, then reliability is improved, but productivity decreases
Solution Approach 1:
The patent changes the verification parameter by introducing group-specific verify voltages that correspond to different target program states. Instead of using a single verify voltage for all cells, each target group receives verification at its appropriate voltage level. This parameter differentiation ensures reliable verification for each cell type while reducing the total number of verification cycles required.
Solution Approach 2:
The patent performs preliminary grouping of memory cells into target groups based on their desired program states before the verification process. This preliminary classification allows the verification operation to be optimized for each group, enabling parallel processing and reducing the total verification time while maintaining high reliability through targeted verification.
3Device complexity
If a single verify voltage is used for all memory cells, then device complexity is reduced, but manufacturing precision deteriorates
Solution Approach 1:
The patent implements local quality by assigning different verify voltages to different target groups of memory cells. Each group receives verification at a voltage level optimized for its target program state, enabling precise verification of different program states while maintaining manageable circuit complexity through systematic voltage assignment.
Solution Approach 2:
The patent introduces dynamic verification voltage selection based on the target program state of the memory cells being verified. The verification circuit dynamically switches between different verify voltages corresponding to different target groups, allowing precise verification across multiple program states without requiring multiple fixed verification circuits.
Data Source
AI summary
The present disclosure provides an operation method of a memory, a memory, and a memory system, and relates to the technical field of memory technology. An example method includes: at a first program stage, performing a program operation on memory cells of a target group including a first memory cell and a second memory cell for a first number of times, wherein the first memory cell and the second memory cell have different target program states, then performing a verify operation using a verify voltage for the target group; and after the second memory cell passes the verification that uses the verify voltage for the target group, performing the program operation on the second memory cells for a second number of times, and inhibiting the second memory cell from being verified.