Flash Memory Programming Voltage Control
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Solution Overview
Problem
Current flash memory devices face challenges in efficiently operating and reducing power consumption, particularly during programming operations, which affects their performance and reliability in various electronic devices.
Innovation Solution
The proposed memory device employs a control circuit that manages voltages across multiple word lines to perform programming operations by initially turning off and then turning on specific switch cells, boosting voltages in channel regions, and varying switch voltages to prevent hot carriers from interfering with adjacent memory cells, thereby optimizing the programming process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If conventional programming operations are used in flash memory devices, then programming functionality is achieved, but power consumption is high and interference with peripheral memory cells occurs
Solution Approach 1:
The patent segments the programming operation into multiple phases (first programming phase and second programming phase) with different voltage levels. In the first phase, a first programming voltage is applied to program memory cells. In the second phase, a second programming voltage (higher than the first) is applied to complete programming. This segmentation allows efficient programming while controlling power consumption by applying higher voltages only when necessary.
Solution Approach 2:
The patent dynamically adjusts the programming voltage levels based on the programming phase and memory cell location. The control circuit varies the voltage applied to word lines corresponding to different memory cell strings, applying higher voltages to upper portion word lines and lower voltages to lower portion word lines. This dynamic voltage adjustment optimizes programming efficiency while reducing overall power consumption.
2Productivity
If high programming voltages are applied to all word lines simultaneously, then programming speed is improved, but interference with peripheral memory cells increases
Solution Approach 1:
The patent applies different voltage levels to different word lines based on their location in the memory array. Word lines corresponding to upper portion memory cell strings receive higher programming voltages, while word lines for lower portion strings receive lower voltages. This local differentiation ensures that high voltages only affect the intended target memory cells, preventing interference with peripheral memory cells in other regions.
Solution Approach 2:
The patent divides the memory array into multiple segments (upper portion and lower portion) and applies different voltage levels to each segment during programming operations. This segmentation allows simultaneous programming of multiple memory cells at different voltage levels, improving overall programming speed while preventing voltage-induced interference in non-target regions.
3Productivity
If switch cells are turned on early in the programming operation, then programming efficiency is improved, but hot carriers may interfere with adjacent memory cells
Solution Approach 1:
The patent performs preliminary actions by first programming memory cells using a lower voltage level before applying higher voltages to complete the programming operation. The control circuit sequentially activates switch cells and applies voltages in a controlled sequence, ensuring that hot carriers generated during low-voltage programming do not interfere with adjacent memory cells before the higher voltage programming phase begins.
Solution Approach 2:
The patent dynamically controls the timing and sequence of switch cell activation and voltage application. The control circuit varies the timing of switch cell turn-on and voltage level changes based on the programming phase, ensuring that switch cells are activated at optimal moments when hot carrier interference is minimized, thereby improving programming efficiency while preventing interference.
Data Source
AI summary
A memory device includes a memory cell array including a first switch cell, a second switch cell, and a plurality of memory cells disposed between the first the second switch cells and connected to a plurality of word lines, and a control circuit configured to perform a program operation by providing a program voltage to a first word line among the plurality of word lines, a switch voltage to a second word line among the plurality of word lines, and a pass voltage to remaining word lines among the plurality of word lines, wherein the control circuit is configured to turn off the first switch cell and the second switch cell in a first section of the program operation, and configured to turn on the first switch cell and increase the switch voltage in a second section of the program operation later than the first section.