Flash Memory PUF Key Generation via Dynamic Read Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current technologies lack a method to generate secure keys using memory devices without requiring significant correction, specifically for physical unclonable functions (PUF) in authentication and security applications.
Innovation Solution
A flash memory apparatus with a physical unclonable function (PUF) that generates a unique response value by using a flash memory unit with a main and peripheral memory area, where the peripheral area stores setting data and includes memory cells with different threshold voltage values, allowing for a read voltage to be set based on a challenge value to produce a random response value.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PUF technologies using SRAM, ring oscillators, or latches are used, then unique keys can be generated based on physical characteristics, but separate significant correction is required within the memory
Solution Approach 1:
The patent combines the PUF cell array with the memory structure, merging the PUF functionality directly into the memory device. The memory cell array serves dual purposes: storing data and generating PUF keys, eliminating the need for separate correction mechanisms and reducing overall system complexity.
Solution Approach 2:
The memory device is designed to perform multiple functions: data storage and PUF key generation. The same memory cell array is used for both purposes, with the PUF key generation utilizing the inherent physical variations of the memory cells without requiring separate correction circuits.
2Reliability
If a separate PUF system is implemented, then PUF functionality is achieved, but it requires additional components and correction mechanisms
Solution Approach 1:
The patent merges the PUF system with the memory structure by using the memory cell array as the PUF cell array. This integration eliminates separate PUF components and correction mechanisms, reducing system complexity while maintaining PUF functionality.
Solution Approach 2:
The memory device serves dual purposes: data storage and PUF key generation. The control unit manages both functions, and the same physical infrastructure (memory cells, word lines, bit lines) is used for both operations, eliminating the need for separate PUF system components.
3Ease of operation
If read voltage is fixed for memory cells, then simple reading is achieved, but random response values cannot be generated for PUF
Solution Approach 1:
The patent introduces dynamic read voltage selection based on challenge values. The control unit adjusts the read voltage applied to memory cells according to the incoming challenge, enabling the system to generate random response values while maintaining operational simplicity through automated voltage management.
Solution Approach 2:
The read voltage parameter is changed dynamically based on the challenge value input. By varying the read voltage, the system exploits the threshold voltage variations in memory cells to generate random response values, transforming a static reading operation into a dynamic PUF key generation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the security of PUF keys by utilizing the physical characteristics of memory cells to generate unique response values, improving security without the need for separate corrections.
Implementation Method 1
The pre-set memory area consists of a plurality of memory cells including two or more memory cells having different threshold voltage values
Data Source
AI summary
A flash memory apparatus having a physical unclonable function (PUF) and an embodying method of the same are provided. To elaborate, the flash memory apparatus includes a flash memory unit that comprises a main memory area and a peripheral memory area; a challenge input unit that receives input of a challenge value; a read voltage setting unit that sets a read voltage based on the input challenge value; a data reading unit that reads data by applying the read voltage to a memory cell included in a pre-set memory area in the peripheral memory area each time the challenge value is input; and a response output unit that outputs the read data as a response value corresponding to the challenge value, wherein the pre-set memory area consists of a plurality of memory cells comprising two or more memory cells having different threshold voltage values.