Flash Memory Access with Batched RAID ECC Buffering

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Solution Overview

Problem

Flash memory cells can malfunction due to particles or mask defects during manufacturing, leading to failures in accessing storage units, which can result in data loss and require methods to protect stored data.

Innovation Solution

A method involving a multiplexer, buffer, and RAID-encoding unit is used to couple DRAM to a buffer, store messages, and generate both vertical and horizontal ECCs, allowing for reliable access and storage of data by coupling the RAID-encoding unit to the buffer and outputting ECCs in batches, enabling error correction and data protection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If flash memory cells are manufactured with standard processes, then manufacturing cost is reduced, but particles or mask defects cause storage unit failures and data loss

Engineering Contradiction:
Improvemanufacturing costVSAvoidstorage unit access reliability
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The patent applies preliminary action by generating and storing vertical ECCs before data access operations. The system pre-calculates error correction codes for each storage unit and stores them alongside the data. When a storage unit malfunction occurs due to particles or mask defects, the pre-stored vertical ECCs enable immediate error correction without requiring re-manufacturing or complex recovery procedures, thus maintaining reliability while using standard manufacturing processes

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent implements beforehand cushioning by creating a protective layer of vertical ECCs that cushion against potential storage unit failures. These ECCs act as a safety buffer that absorbs the impact of manufacturing defects (particles or mask defects) before they can cause complete data loss. The vertical ECCs are stored in separate memory cells, providing a protective mechanism that allows the system to withstand manufacturing imperfections without compromising data integrity

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

2Reliability

If vertical ECCs are generated and stored for every storage unit, then data protection capability is improved, but memory resources and writing overhead increase

Engineering Contradiction:
Improvedata protection capabilityVSAvoidmemory resources and writing overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the error correction mechanism into vertical ECCs (stored with each storage unit) and horizontal ECCs (generated across multiple storage units). This segmentation allows the system to provide comprehensive data protection while distributing the overhead across different layers. The vertical ECCs handle individual storage unit failures, while horizontal ECCs handle broader patterns of failures, thereby managing memory resources efficiently through hierarchical error correction

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements partial action by generating vertical ECCs only for storage units that require protection based on assessed risk or access patterns, rather than uniformly for all storage units. The system can selectively apply vertical ECC generation to critical storage units or those more susceptible to manufacturing defects, thereby providing adequate data protection capability while reducing the overall memory overhead and writing overhead to manageable levels

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS9459962B2Methods for accessing a storage unit of a flash memory and apparatuses using the same
Publication Date: 2016.10.04 SILICON MOTION INC
  • US9459962B2 patent drawing
  • US9459962B2 patent drawing
  • US9459962B2 patent drawing

AI summary

An embodiment of a method for accessing a storage unit of a flash memory, performed by a processing unit, includes at least the following steps. A multiplexer is controlled to couple a DRAM (Dynamic Random Access Memory) to a buffer. A DMA (Direct Memory Access) controller is directed to store a message of the DRAM to the buffer through the multiplexer and to output the message of the DRAM to a RAID-encoding (Redundant Array of Independent Disk-encoding) unit in multiple batches. After a first condition is satisfied, the processing unit controls the multiplexer to couple the RAID-encoding unit to the buffer and directs the RAID-encoding unit to output a vertical ECC (Error Correction Code) to the buffer through the multiplexer in at least one batch.