Flash Memory Cell with Raised Source Drain and Charge Trapping Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reliability of flash memory cells is compromised by current leakage due to defects in the tunneling oxide layer of traditional ETOX cells, leading to reduced erasure efficiency and device performance.
Innovation Solution
A SONOS flash memory cell structure is developed with charge-trapping spacers on the sidewalls of raised source/drain regions, utilizing a composite oxide/nitride/oxide (ONO) layer for localized charge storage, allowing independent tuning of gate oxide and spacer layers for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a polysilicon floating gate is used in ETOX cells, then programming capability is achieved through channel hot-electron effects, but current leakage occurs due to defects in the tunneling oxide layer
Solution Approach 1:
The patent extracts the charge storage function from the polysilicon floating gate and relocates it to the nitride layer within the ONO spacer structure. This separation allows the tunneling oxide to serve solely as an insulating barrier without the complexity of a polysilicon gate, thereby reducing current leakage while maintaining programming capability through hot-electron injection into the nitride layer
Solution Approach 2:
The patent employs a composite oxide/nitride/oxide (ONO) spacer structure where the nitride layer serves as the charge storage medium and the oxide layers provide electrical isolation. This composite structure replaces the traditional polysilicon floating gate, achieving both reliable charge storage and reduced current leakage through the inherent properties of the dielectric materials
2Ease of manufacture
If the gate oxide layer and charge-trapping spacers are formed together, then manufacturing process is simplified, but rule limitation affects both layers reducing fabrication flexibility
Solution Approach 1:
The patent segments the formation process into two independent stages: first forming the gate oxide layer, then separately forming the ONO charge-trapping spacers. This segmentation allows each layer to be optimized independently according to its specific requirements without being constrained by common lithographic rules, thereby achieving both ease of manufacture and high adaptability
Solution Approach 2:
The gate oxide layer is formed in advance as a preliminary step before forming the ONO spacers. This preliminary action establishes a stable foundation that is not affected by subsequent spacer formation processes, allowing independent optimization of each layer's thickness and properties while maintaining a streamlined manufacturing workflow
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances erasure efficiency by concentrating electron distribution at separate trapping regions, reducing local electrical field effects and current leakage, while maintaining compatibility with CMOS manufacturing processes.
Implementation Method 1
The charge trapping layer is comprised of silicon oxide/nitride/silicon oxide (ONO) layers. Since the charge trapping layer is a dielectric layer, the hot carriers injected into the charge trapping layer are localized and have a Gauss distribution.
Implementation Method 2
The ETOX cell is programmed by channel hot-electron (CHE) effects and is erased by Fowler-Nordheim (F-N) tunneling effects through the source side.
Data Source
AI summary
A method for forming a flash memory cell and the structure thereof is disclosed. The flash memory cell includes a substrate, a first raised source/drain region and a second raised source/drain region separated by a trench in-between, a first charge-trapping spacer and a second charge-trapping spacer respectively on the sidewall of the first and second raised source/drain region, a gate structure covering the first and second spacers, the trench and the first and second raised source/drain regions and a gate oxide layer located between the gate structure and the first and second raised source/drain regions and the substrate. By forming the charge-trapping spacers with less e-distribution, the flash memory affords better erasure efficiency.