Flash Memory as Main RAM via OS Kernel Buffering
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Solution Overview
Problem
Conventional DRAM technology is not suitable for high-speed applications due to bandwidth issues, making it difficult to directly substitute with existing DRAM applications, despite FLASH memory offering advantages like lower power consumption and higher density.
Innovation Solution
Operating system kernel enhancements are implemented to recognize FLASH memory as a main memory component, accounting for its nuances such as longer write times and segmented updates, by using a buffer to manage access between FLASH and DRAM, allowing for background updates and mitigating latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If FLASH memory is used to replace DRAM for main memory applications, then power consumption is reduced and storage density is increased, but write speed and access latency are worsened due to longer programming times and segmented update requirements
Solution Approach 1:
The patent introduces a buffer component as an intermediary between the processor and FLASH memory. This buffer temporarily stores data during write operations, allowing the processor to continue executing instructions without waiting for the slow FLASH programming process to complete, thereby maintaining system speed while using energy-efficient FLASH memory
Solution Approach 2:
The system performs preliminary actions by pre-allocating buffer space and pre-processing data before writing to FLASH memory. The buffer is prepared in advance to accommodate incoming data, and data is staged in the buffer before the actual FLASH programming operation begins, reducing overall write latency
2Quantity of substance
If FLASH memory is used for main memory applications, then storage density is increased and cost is reduced, but system complexity increases due to the need for buffer management and timing coordination
Solution Approach 1:
The buffer component serves multiple functions: it acts as temporary storage during write operations, masks the speed difference between processor and FLASH, manages data staging, and coordinates timing between different system components. This multi-functionality reduces the need for additional specialized components, thereby limiting the increase in system complexity
3Reliability
If FLASH memory programming operations are performed, then data is stored permanently with high density, but program operations may stall due to latency and sequential update requirements
Solution Approach 1:
The patent segments the memory system into two distinct parts: a fast buffer region for active data manipulation and a permanent FLASH region for reliable storage. This segmentation allows write operations to be divided into immediate buffer writes that don't stall execution and background FLASH programming that ensures data retention without impacting real-time operations
Data Source
AI summary
A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.