3D Flash Memory Threshold Voltage Control
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Solution Overview
Problem
Three-dimensional stacked flash memory devices face issues with random telegraph noise and lateral charge migration, leading to fluctuations in threshold voltage and increased read errors due to shared charge trapping layers, which reduce the reading window.
Innovation Solution
A memory device with a control circuit that performs multiple write and verification operations to ensure target memory cells meet preset threshold voltage criteria, using incremental step pulse programming and adjusted verification voltages to correct voltage offsets and reduce read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensional stacked flash memory is used to increase storage capacity, then storage capacity is improved, but threshold voltage fluctuation and read errors increase due to random telegraph noise and lateral charge migration
Solution Approach 1:
The patent performs a first write verification operation immediately after the write operation to detect threshold voltage deviations caused by lateral charge migration and random telegraph noise. This preliminary detection allows the system to identify memory cells that require compensation before they can cause read errors, thus maintaining reliability while preserving the high storage capacity of three-dimensional stacked flash memory.
Solution Approach 2:
The patent implements a feedback mechanism where the write verification operation results are used to determine whether a second write operation with adjusted verification voltage is needed. If the failure bit count exceeds a threshold, the system adjusts the verification voltage and performs additional write operations to compensate for threshold voltage shifts, thereby correcting reliability issues while maintaining the high-density storage structure.
2Reliability
If multiple write verification operations are performed to reduce read errors, then read error rate is improved, but write operation time increases
Solution Approach 1:
The patent performs the second write operation and verification only when necessary - specifically when the failure bit count from the first verification exceeds a predetermined threshold. This conditional approach applies additional verification actions only to memory cells that exhibit threshold voltage deviations, avoiding unnecessary write operations on already reliable cells and thus minimizing the increase in total write operation time while still reducing read errors.
3Manufacturing precision
If adjusted verification voltage is used to correct threshold voltage offsets, then threshold voltage distribution accuracy is improved, but operation complexity increases
Solution Approach 1:
The patent adjusts the verification voltage parameter based on the results of the first write verification operation. When threshold voltage deviations are detected (failure bit count exceeds threshold), the system changes the verification voltage parameter for the second write operation to compensate for the offsets. This dynamic parameter adjustment improves threshold voltage distribution accuracy while maintaining relatively simple operation logic through automated conditional execution.
Data Source
AI summary
A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.