Flash Memory Read Failure Diagnosis via Adjusted Voltage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices experience read failures due to charge leakage, soft-programming, and over-programming, which are difficult to diagnose and repair without exacerbating the issue, as current methods may worsen the problem if the cause is not accurately identified.
Innovation Solution
A memory controller with an error correction unit is used to analyze read failures and perform additional read operations with adjusted voltages to determine the cause, allowing for targeted repair through charge refresh or increased de-selective read voltage based on the identified issue.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If additional read operations with adjusted voltages are performed to diagnose read failures, then diagnostic accuracy is improved, but operation time increases
Solution Approach 1:
The diagnostic process is segmented into multiple distinct read operations, each targeting a specific failure cause (charge leakage, soft-programming, over-programming). By dividing the diagnosis into separate operational stages with different voltage conditions, the system achieves comprehensive diagnostic accuracy while maintaining structured efficiency.
Solution Approach 2:
The system performs preliminary read operations with standard voltages before escalating to adjusted voltage conditions. This staged approach allows the system to quickly identify obvious failures while reserving more time-consuming adjusted voltage operations for cases where they are truly necessary, thereby optimizing the time-accuracy tradeoff.
2Productivity
If repair operations are performed without accurate diagnosis, then operation speed is improved, but reliability deteriorates due to potential exacerbation of the problem
Solution Approach 1:
The system implements a feedback mechanism where the results of each read operation (including error correction unit outputs) are analyzed to determine the next diagnostic or repair step. This closed-loop approach ensures that repair operations are based on accurate failure cause identification, preventing exacerbation of the problem while maintaining efficient operation.
Solution Approach 2:
The system performs preliminary diagnostic read operations before executing any repair actions. This ensures that the root cause of the read failure is accurately identified (charge leakage, soft-programming, or over-programming) before applying the appropriate repair strategy, thereby maintaining both speed and reliability.
3Adaptability or versatility
If multiple read operations with different voltages are performed, then diagnostic capability is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle multiple diagnostic and repair operations through a unified interface. The same controller hardware performs standard reads, adjusted voltage reads, error correction, and repair operations, eliminating the need for separate dedicated circuits for each function and thereby managing complexity while maintaining versatile diagnostic capability.
Solution Approach 2:
The system diagnoses different failure causes by changing voltage parameters (selective read voltage, de-selective read voltage) rather than by adding complex hardware. This parameter-based diagnostic approach allows the same physical device to adapt to different diagnostic needs through software-controlled voltage adjustments, maintaining hardware simplicity while achieving high diagnostic versatility.
Data Source
AI summary
Semiconductor memory devices are provided that include a nonvolatile memory that has a plurality of memory cells and a memory controller that is configured to control at least some of the operations of the nonvolatile memory. The memory controller include an error correction unit. Moreover, the memory controller is configured to determine whether a read failure that occurs during a read operation of a first of the plurality of memory cells is due to charge leakage based at least in part on an output of the error correction unit. Related methods are also disclosed.


