Flash Memory Read-Reclaim Decision Logic Using Cell-Level Error Direction
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Solution Overview
Problem
Read disturb in NAND flash memory devices leads to increased errors and reduced endurance due to the performance of read-reclaim operations, which are currently determined solely by bit-errors without considering the direction of cell-level errors.
Innovation Solution
A method that assesses the need for read-reclaim operations by evaluating the difference in cell-errors in the direction of increasing and decreasing cell-levels, using error correction decoding to determine the programmed and corrected data states of memory cells, and performing a read-reclaim operation based on these counts to avoid unnecessary operations and enhance endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If read-reclaim operations are performed based on bit-error thresholds, then data integrity is maintained, but unnecessary operations increase reducing memory endurance
Solution Approach 1:
The patent changes the parameter used for decision-making from simple bit-error count to a more sophisticated metric that considers the direction of cell-level errors (e+ and e-). By analyzing whether errors are increasing or decreasing in specific directions, the system can more accurately predict future read-disturb impacts and avoid unnecessary read-reclaim operations, thus preserving memory endurance while maintaining data integrity.
Solution Approach 2:
The patent implements a feedback mechanism where the controller continuously monitors error patterns (e+ and e- counts) from read operations and uses this information to predict future block health. This feedback loop enables intelligent decision-making about when read-reclaim is truly necessary, reducing unnecessary operations that would otherwise harm endurance while still protecting against actual degradation.
2Reliability
If read-reclaim operations are performed frequently to ensure data integrity, then error rates are reduced, but operation overhead increases reducing productivity
Solution Approach 1:
Instead of performing read-reclaim operations frequently or uniformly across all blocks, the patent applies partial action by selectively performing operations only on blocks that show specific error patterns (high e+ combined with low e-). This targeted approach reduces overall operation overhead while maintaining sufficient error protection for blocks that actually need it.
Solution Approach 2:
The patent introduces new parameters (e+ and e- error counts and their differential) to replace the traditional single threshold parameter. This enables more nuanced decision-making that distinguishes between blocks requiring immediate read-reclaim and those that can tolerate additional read operations, thereby reducing unnecessary overhead while maintaining data integrity where critical.
3Device complexity
If simple bit-error thresholding is used to determine read-reclaim, then decision complexity is reduced, but measurement precision of block health deteriorates
Solution Approach 1:
The patent segments the error analysis into two distinct components: e+ (errors in one direction) and e- (errors in the opposite direction). By dividing the error measurement into these segments, the system gains more precise information about block health trends without creating excessive overall complexity. The segmentation allows the controller to understand whether errors are increasing or decreasing, providing better measurement precision while maintaining manageable decision logic.
Solution Approach 2:
The patent applies asymmetry by treating e+ and e- errors differently rather than counting all errors uniformly. The decision logic specifically looks for asymmetric patterns (high e+ with low e-) that indicate impending read-disturb problems. This asymmetric approach improves measurement precision by focusing on the specific error patterns that matter most, while the asymmetry itself provides a clear, intuitive decision criterion that doesn't overly complicate the control logic.
Data Source
AI summary
A system includes a plurality of memory cells. Each memory cell is programmed to a data state corresponding to one of multiple cell programmed voltages. The memory cells are read to determine a programmed data state of each memory cell. Error correction decoding is performed to determine a corrected data state of each memory cell. The corresponding cell levels, or programmed voltages, are determined based on the programmed data state and the corrected data state. A first error count represents a total number of error cells that have a higher cell level for the corrected data state than the programmed data state. A second error count represents a total number of error cells that have a lower cell level for the corrected data state than the programmed data state. The system is configured to perform a memory operation based on the first error count and the second error count.