Flash Memory Read Voltage Optimization via Iterative Error Adjustment
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Solution Overview
Problem
Flash memory systems face increased latency and errors due to threshold voltage drift over time, leading to multiple retries and longer read times, especially in aging flash memory or long-term storage.
Innovation Solution
A method is introduced to bias the read voltage for flash memory by determining and adjusting the optimum read voltage level based on bit errors, iteratively refining the voltage to minimize errors, thereby optimizing read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a default read voltage is used until errors become unacceptable, then device simplicity is maintained, but read latency increases due to multiple retries
Solution Approach 1:
The system performs preliminary action by proactively monitoring bit error rates and adjusting read voltage before errors become unacceptable. The storage system continuously determines bit error rates for read operations and iteratively adjusts the read voltage level to compensate for threshold voltage drift, preventing read failures before they occur rather than waiting for errors to accumulate and then retrying with different voltages.
Solution Approach 2:
The system implements feedback by continuously monitoring the bit error rate of read operations and using this information to dynamically adjust the read voltage level. The storage system determines a bit error rate for read operations, compares it against thresholds, and iteratively adjusts the read voltage up or down based on whether the error rate is too high or acceptable, creating a closed-loop control system that maintains optimal read performance.
2Reliability
If read voltage is adjusted dynamically to compensate for threshold voltage drift, then read reliability improves, but device complexity increases
Solution Approach 1:
The storage system performs self-service by autonomously monitoring its own read operations, detecting threshold voltage drift through bit error rate analysis, and automatically adjusting the read voltage level without external intervention. The system determines bit error rates for read operations, identifies when drift occurs, and iteratively adjusts the read voltage to compensate, enabling the system to self-correct and maintain reliability without requiring complex external control mechanisms.
3Measurement precision
If multiple read voltage levels are tested to find optimum voltage, then read accuracy improves, but read time increases
Solution Approach 1:
The system applies dynamics by making the read voltage level adjustable and adaptable rather than fixed. The storage system iteratively adjusts the read voltage level based on monitored bit error rates, allowing the voltage to dynamically respond to threshold voltage drift. This dynamic adjustment enables the system to maintain optimal read accuracy without requiring exhaustive testing of multiple voltage levels each time a read operation occurs.
Data Source
AI summary
A method for biasing read voltage for flash memory in a storage system, performed by the storage system, is provided. The method includes determining a first number of bit errors for a first read of data at an address in the flash memory at a previously determined optimum read voltage level. Determining a second number of bit errors for a second read of the data at the address in the flash memory at a further read voltage level. Adjusting the optimum read voltage level up or down based on a comparison of the first number of bit errors and the second number of bit errors. Iterating each method operation, to adjust the optimum read voltage level in a first direction of the further read voltage level when the second number of bit errors is less than the first number of bit errors, and to adjust the optimum read voltage level in a second direction when the second number of bit errors is greater than the first number of bit errors.