Embedded Flash Memory Data Reading Circuit Switch Control
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Solution Overview
Problem
The existing data reading circuits for embedded flash memory cells fail to function properly due to insufficient switch control voltage, leading to a failure in connecting the switch circuit, which affects the reliability of data reading, especially in the 55 nm process where the core device voltage is 1.2V+/â10% and threshold voltage is 0.6V for high-threshold N channels.
Innovation Solution
A data reading circuit is designed with a switch circuit, current clamp circuit, current mirror circuit, precharge circuit, and comparison circuit, along with a second switch control voltage generation module, utilizing transmission gates, NMOS and PMOS transistors, and capacitors to ensure normal connection of the data node and bit line by applying appropriate control voltages, thereby overcoming the issue of insufficient switch control voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional reading circuit with single voltage control is used, then circuit simplicity is maintained, but switch connection reliability fails when control voltage is insufficient
Solution Approach 1:
The patent divides the switch control function into two independent voltage control inputs (first switch control voltage and second switch control voltage) for the transmission gate. This segmentation allows each voltage to independently control different aspects of the switch operation, ensuring reliable connection even when individual voltages are insufficient alone.
Solution Approach 2:
The patent applies preliminary action by pre-charging the data node to a first voltage level before the actual reading operation. This preliminary voltage establishment ensures that when the transmission gate switches on, the data node is already in the correct voltage state, preventing connection failures due to voltage insufficiency.
2Reliability
If dual voltage control is applied to transmission gate, then switch connection reliability is improved, but control circuit complexity increases
Solution Approach 1:
The transmission gate is designed to accept multiple control voltages (first and second switch control voltages) that can serve different functions: one for enabling the switch and another for ensuring proper voltage level. This multi-functionality allows a single transmission gate structure to handle multiple control requirements, improving connection reliability without requiring separate switch structures.
Solution Approach 2:
The patent introduces an intermediate voltage level (first voltage) for the data node that acts as a mediator between the power supply voltage and the actual data signal. This intermediate voltage ensures proper switching operation and signal level matching, facilitating reliable connection between the data node and bit line while managing voltage level transitions smoothly.
3Reliability
If switch control voltage is increased to ensure connection, then connection reliability improves, but power consumption increases
Solution Approach 1:
The patent applies partial action by using two separate control voltages with different magnitudes: the first switch control voltage can be lower (insufficient to fully turn on the transmission gate alone), while the second switch control voltage provides the additional drive needed. This partial action approach ensures reliable switching without requiring both voltages to be excessively high, thus managing power consumption effectively.
Solution Approach 2:
The patent changes the voltage parameters by introducing dual voltage control instead of single voltage control. The first and second switch control voltages have different characteristics and can be optimized independently, allowing the system to achieve reliable connection while minimizing overall power consumption by selecting appropriate voltage levels for each control input.
Data Source
AI summary
The application relates to a data reading circuit of an embedded flash memory cell. The data reading circuit a switch circuit, a current clamp circuit, a current mirror circuit, a reference current source, a precharge circuit and a comparison circuit; the switch circuit includes a transmission gate, one end of the transmission gate is connected with a drain of the embedded flash memory cell, and the other end of the transmission gate is connected with a detection end of the current clamp circuit; a response end of the current clamp circuit is connected with a data node; the current mirror circuit is connected with the reference current source and the data node; an output end of the precharge circuit is connected with the data node; one input end of the comparison circuit is connected with the data node, and the other input end is connected with reference voltage.