Flash Memory Ready/Busy Signal Logic Mechanism
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Solution Overview
Problem
Existing flash memory devices lack efficient hardware-based monitoring of operation, particularly in providing two logical 'Ready/Busy' indications, which increases complexity and reduces time-efficiency for the Host device, and are not compliant with the standard NAND flash interface.
Innovation Solution
A flash memory device with a logic mechanism that outputs two logical 'Ready/Busy' indications as a single hardware signal, allowing the Host device to select conditions for the signal based on operations or failures, ensuring compatibility with the standard NAND flash interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two logical 'Ready/Busy' indications are provided separately, then the Host device can monitor both cache buffer and memory array states, but the device complexity and monitoring complexity increase
Solution Approach 1:
The patent combines two separate Ready/Busy signals (Cache Ready/Busy and Array Ready/Busy) into a single unified signal. The logic mechanism internally selects which condition drives the single signal based on the operation type, merging the monitoring function while maintaining the ability to distinguish between cache and array states.
Solution Approach 2:
The single Ready/Busy signal serves multiple functions by dynamically changing its logical meaning based on the operation type. For read operations, it indicates array status; for program operations, it indicates cache buffer status. This multi-functional approach eliminates the need for separate signals while preserving comprehensive monitoring capability.
2Ease of operation
If software polling is used to monitor status, then the Host device can determine operation completion, but the time efficiency decreases
Solution Approach 1:
The patent implements a hardware-based feedback mechanism where the Ready/Busy signal automatically changes state to notify the Host device when operations complete. This active feedback eliminates the need for continuous software polling, reducing CPU overhead and wait time while maintaining simple monitoring through interrupt-driven or event-driven approaches.
3Productivity
If a cache buffer is added for simultaneous data transfer, then the system throughput increases, but the device complexity increases
Solution Approach 1:
The patent implements a dynamic Ready/Busy signal that changes its logical meaning based on the operation type and internal state. The signal adapts its function to reflect either cache buffer status or memory array status depending on the current operation, allowing the system to manage complex buffer architecture dynamically without requiring separate static signals for each component.
4Ease of manufacture
If the Ready/Busy signal logic is fixed, then the interface is simple, but the adaptability to different operation types decreases
Solution Approach 1:
The patent employs a dynamic logic mechanism that selects which condition (cache busy or array busy) drives the Ready/Busy signal based on the operation type. This dynamic adaptation allows a single fixed physical signal to serve multiple operation types effectively, maintaining interface simplicity while achieving full adaptability to different flash memory operations.
Data Source
AI summary
A flash memory device includes an array of memory cells for storing data pages, at least one buffer (e.g. a memory buffer and a cache buffer) for transferring the data pages to and from the array of memory cells and a host, and an output pin. A logic mechanism is operative to select, from among a plurality of conditions related to an operation on the array of memory cells, a condition that drives a signal being output on the output pin. A data page transfer by the host is contingent on the signal being output on the output pin.