Flash Memory Recess Formation Using Polysilicon Spacer Depth Control
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Solution Overview
Problem
In NAND flash memory devices with 70 nm or less, significant interference between floating gates occurs, making it difficult to improve yield and reliability due to complex manufacturing processes and challenging thickness control in conventional methods.
Innovation Solution
A method involving the formation of a tunnel oxide layer and polysilicon layer over a semiconductor substrate, followed by a trench formation and isolation layer deposition, with a polysilicon spacer layer used to etch a recess hole in the isolation layer, reducing the number of etch steps and allowing precise depth control using an amorphous-carbon spacer layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional multiple etch process steps are used to form recesses in isolation layer, then thickness control becomes more difficult and process complexity increases, but yield and reliability cannot be improved
Solution Approach 1:
A polysilicon spacer layer is introduced as an intermediary structure to define the recess depth. The spacer layer is formed on the isolation layer, and a single etch process removes the spacer layer and isolation layer down to the substrate surface, using the spacer thickness as a precise depth reference. This eliminates the need for multiple etch steps while maintaining accurate depth control.
Solution Approach 2:
The polysilicon spacer layer is formed in advance before the recess etching process. By pre-forming the spacer with a controlled thickness that corresponds to the desired recess depth, the subsequent etch process can be performed in a single step with precise depth control, avoiding the need for multiple iterative etch steps.
2Reliability
If conventional manufacturing process is used, then process steps are numerous and thickness control is difficult, but interference between floating gates cannot be sufficiently reduced
Solution Approach 1:
The polysilicon spacer layer serves as a mediator that precisely defines the recess geometry. By forming the spacer with controlled thickness and using it as a mask during etching, the recess depth and shape are precisely controlled, ensuring adequate separation between floating gates to reduce interference while simplifying the overall process.
Solution Approach 2:
The invention changes the approach from controlling recess depth through multiple etch parameters to controlling it through the spacer layer thickness parameter. This single parameter control method simplifies the process while achieving the required precision for reducing floating gate interference.
Data Source
AI summary
A method of manufacturing a flash memory device includes the steps of forming a tunnel oxide layer and a polysilicon layer over a semiconductor substrate. An etch process is then performed to form a pattern and a trench. An isolation layer is formed in the trench. A polysilicon spacer layer is formed on the resulting surface. A specific region of the polysilicon spacer layer and the isolation layer is etched in a single etch process to form a recess hole in a central portion of the isolation layer. The polysilicon spacer layer is then removed.