Flash Memory Recorder Hybrid Redundancy Overhead
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Solution Overview
Problem
Conventional methods for achieving high reliability in flash memory data recorders, such as those used in space missions, are costly, power-intensive, and inefficient due to the need for triple modular redundancy, which triples storage requirements and increases overhead.
Innovation Solution
A hybrid approach combining error correction at the individual word level with 'warm spare' redundancy at the page, block, or component level, using error count lookup tables to manage bad blocks and implement warm spare replacement, reducing overhead to 1.5 times the actual data storage while maintaining robust reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If triple modular redundancy is used to achieve high reliability, then reliability is improved, but storage overhead increases to three times the actual data storage
Solution Approach 1:
The patent segments the redundancy mechanism into two distinct components: error correction code (ECC) for bit-level error correction and warm spare blocks for block-level replacement. This segmentation allows each component to operate at its optimal level, with ECC handling minor bit flips and warm spares handling larger block failures, thereby reducing the total redundancy overhead compared to uniform triple modular redundancy
Solution Approach 2:
The patent changes the parameter of redundancy representation from fixed triple modular redundancy to a dynamic hybrid scheme where the amount of redundancy is adjusted based on actual error patterns. The warm spare mechanism allows selective replacement of failed blocks, and the system monitors error counts to dynamically manage when to use ECC versus when to activate warm spare replacement, optimizing the reliability-to-overhead ratio
2Reliability
If triple modular redundancy is used to achieve high reliability, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic monitoring of error counts in the flash memory blocks through the embedded microcontroller. The system periodically checks error patterns and selectively activates warm spare replacement only when necessary, rather than continuously maintaining all redundant paths active. This periodic action reduces power consumption by keeping the system in a lower-power state during normal operation and only activating full redundancy mechanisms when errors are detected
Solution Approach 2:
The system incorporates an embedded microcontroller that autonomously monitors error counts, manages the lookup tables, and controls when to activate warm spare replacement without requiring external intervention. This self-service capability allows the system to maintain high reliability through intelligent error management while consuming less power by avoiding continuous operation of full redundant systems
3Reliability
If triple modular redundancy is used to achieve high reliability, then reliability is improved, but cost increases
Solution Approach 1:
The patent applies partial redundancy by using warm spare blocks that are prepared in advance but only activated when actual failures occur. Rather than maintaining full triple modular redundancy for all blocks simultaneously, the system prepares a smaller set of warm spare blocks that can replace failed blocks as needed. This partial action approach reduces the total amount of redundant hardware required, thereby reducing manufacturing cost while maintaining the ability to achieve high reliability when failures occur
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution decreases storage overhead while providing high reliability, supporting extended mission lengths and maintaining original capacity, with reduced power consumption and cost, by using a combination of error correction and redundancy mechanisms.
Implementation Method 1
a primary magnetoresistant random access memory module communicating with the primary field programmable gate array and comprising a first error count lookup table and a first warm spare replacement lookup table
Implementation Method 2
a primary field programmable gate array comprising a primary static random-access memory module, the primary processor being configured to control operations of the array of high-density flash memory
Data Source
AI summary
The system and method of implementing a high reliability flash memory recorder comprising warm spare and error code correction bytes across several multi-chip modules. The use of redundant field programmable gate arrays and/or processors for command and control increases redundancy. The system and method has lookup table-based mechanisms combined with programming to determine when to substitute a warm spare byte as well as when to declare a block of memory as “bad” and no longer to be used. The system may use multiple memory banks with power switching per bank to reduce power consumption as well as increase reliability when the array is not being accessed.