Flash Memory Reference Word Lines for Sense Amplifier Efficiency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing flash memory apparatuses face inefficiencies in the sense amplifying module, particularly in comparing currents from bit lines and reference bit lines, which affects data read, program, and erase operations due to process variations, requiring a wide reference current range.
Innovation Solution
The implementation of a flash memory apparatus with multiple flash memory array blocks and a sense amplifying module that includes N storage columns, N reference word-line cell units, and reference storage columns, where each storage column has memory cells coupled to word lines and bit lines, and reference word-line cell units are connected to reference word lines and dummy word lines, allowing for the comparison of currents from bit lines and reference bit lines to generate sensing results without the need for a wide reference current range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a wide reference current range is used to accommodate process variations, then the sense amplifying module can handle variations, but the efficiency and performance of the flash memory apparatus deteriorates
Solution Approach 1:
The patent divides the reference current generation into multiple segments by creating N reference storage columns (first reference storage column, second reference storage column, etc.) with different reference bit line cells. Each segment can be independently controlled and selected, allowing the system to accommodate process variations without requiring a single wide reference current range, thus improving sense amplifying module efficiency.
Solution Approach 2:
The patent introduces dynamic control mechanisms where the reference line control circuit can selectively activate different reference storage columns based on process variations. The reference word line control circuit dynamically adjusts which reference bit line cells are active, enabling the system to adapt to varying conditions without sacrificing efficiency.
2Measurement precision
If multiple reference storage columns are added to accommodate process variations, then the sensing ability improves, but the device complexity increases
Solution Approach 1:
The patent designs reference storage columns that serve multiple functions: they provide reference currents for sensing operations, enable process variation compensation, and can be selectively activated based on operational mode. This multi-functionality reduces the need for separate dedicated structures, thereby limiting the increase in device complexity while improving sensing ability.
Solution Approach 2:
The patent embeds multiple reference storage columns within the existing flash memory array structure, integrating them into the word line and bit line architecture. The reference bit line cells are nested within the same physical structure as the main memory cells, allowing the additional reference functionality to be incorporated without proportionally increasing overall device complexity.
Data Source
AI summary
The invention provides a flash memory apparatus including at least one flash memory array block and a sense amplifying module. The flash memory array block comprises N storage columns, N reference word-line cell units and a reference storage column, wherein N is a positive integer. Each of the reference word-line cell units disposed in each of the storage columns, wherein, the reference word-line cell units further coupled to a reference word line and a dummy word line. The reference storage column includes a plurality of reference bit-line cells, the reference word line and the dummy word line, one of the reference bit-line cells which coupled to the reference word line is coupled to a reference bit line. The sense amplifying module compares currents from one of the bit lines and the corresponding reference bit line to generate at least one sensing result.