Flash Memory Block Refresh Cycle Optimization
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Solution Overview
Problem
The reliability of flash memory devices decreases due to rapid charge loss, leading to short retention times, and existing refreshing methods are not flexible enough to address process variations among flash memory blocks, affecting performance and lifespan.
Innovation Solution
A method and apparatus for refreshing flash memory devices that consider process variation by determining a refresh cycle for each block based on its bit error rate and erase cycles, using error-correcting codes to ensure data correctness and reduce wear, and implementing wear leveling by prioritizing blocks with longer refresh cycles for write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refreshing operation is performed frequently to ensure data correctness, then data reliability is improved, but flash memory block wear increases
Solution Approach 1:
The patent dynamically adjusts the refresh cycle parameter based on the actual bit error rate measured from read operations. When the bit error rate is low, the refresh cycle is extended; when the bit error rate exceeds a threshold, the refresh cycle is shortened. This parameter adaptation allows the system to maintain data correctness while minimizing unnecessary refresh operations that cause wear.
Solution Approach 2:
The system performs self-diagnosis by reading data from flash memory blocks and calculating bit error rates through error-correcting code decoding. Based on this self-assessment, the system autonomously determines the appropriate refresh cycle for each block, eliminating the need for conservative uniform refresh schedules and enabling wear-optimized refresh operations.
2Ease of operation
If uniform refresh cycle is applied to all flash memory blocks, then implementation simplicity is maintained, but performance potential is not fully exploited due to process variation
Solution Approach 1:
The patent implements per-block refresh cycle management, where each flash memory block is assigned its own refresh cycle based on its individual bit error rate characteristics. This local customization allows blocks with better retention properties to have longer refresh cycles, while blocks with poorer retention receive more frequent refreshes, thereby maximizing overall memory performance and capacity utilization.
Solution Approach 2:
The refresh cycle for each block is not fixed but dynamically adjusted based on measured bit error rates. The system continuously monitors block health and adapts refresh schedules accordingly, transitioning from static uniform refresh to dynamic personalized refresh patterns that respond to actual block conditions and process variations.
3Reliability
If refresh cycle is shortened to account for process variation, then data retention reliability is improved, but wear speed increases
Solution Approach 1:
The system implements a feedback mechanism where read operations are used to measure the actual bit error rate of each block. This measurement feeds back into the refresh cycle determination logic, allowing the system to identify blocks that truly need frequent refreshes versus those that can tolerate longer intervals. This feedback-driven approach prevents premature or excessive refresh operations on healthy blocks.
Solution Approach 2:
The system performs preliminary data reading and error rate assessment before determining the refresh schedule. By proactively evaluating block health status through read operations and error-correcting code analysis, the system can establish appropriate refresh cycles in advance, avoiding both unnecessary frequent refreshes and inadequate refresh intervals.
Data Source
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AI summary
Embodiments of the present invention provide a method and an apparatus for refreshing a flash memory device, so as to implement optimization of a refresh operation on a flash memory device. The method includes: reading, by a storage controller, first data from a first flash memory block, and determining a bit error rate of the first data; when the bit error rate is greater than a preset threshold, determining, by the storage controller, a refresh cycle of the first flash memory block according to a quantity of erase cycles of the first flash memory block; and performing a refresh operation on the first flash memory block according to the determined refresh cycle. In the embodiments of the present invention, in consideration of process variation among flash memory blocks of a flash memory device, an actual bit error rate of a flash memory block is monitored by using a granularity of per flash memory block, thereby exploiting performance potential of the flash memory block to the greatest extent. Not only correctness of stored data is ensured, but also update of a refresh cycle is postponed to the greatest extent. A speed of wear of the flash memory block because of refresh operations is reduced, thereby improving overall performance of the flash memory device.