Flash Memory Region Segmentation for EEPROM Emulation

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Solution Overview

Problem

Conventional Flash memory systems require larger sizes and higher costs to emulate EEPROM functionality due to the inability to erase data with fine granularity, leading to inefficient use of physical space and increased costs.

Innovation Solution

Configuring Flash memory into a first region for quasi-static data and a second region for frequently updated data, allowing for optimized storage and reduced overall memory size by separating data classes based on update frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If Flash memory is used to emulate EEPROM functionality, then non-volatile storage is achieved, but the required Flash memory size becomes larger than the actual EEPROM size

Engineering Contradiction:
Improvenon-volatile storage capabilityVSAvoidFlash memory size
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The Flash memory is divided into multiple regions (first region and second region) with different access characteristics. The first region stores quasi-static data with infrequent updates, while the second region stores frequently updated data. This segmentation allows the system to accommodate EEPROM emulation requirements without requiring the entire Flash memory to be oversized, thereby reducing the total Flash memory size needed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the Flash memory are assigned different functional characteristics based on data update frequency. The first region is optimized for quasi-static data with rare updates, while the second region is optimized for frequently updated data. This local differentiation of quality allows efficient use of Flash memory space, reducing the overall size required compared to a uniform allocation approach.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If conventional Flash memory emulation schemes are used, then EEPROM functionality is achieved, but system costs increase due to larger memory requirements

Engineering Contradiction:
ImproveEEPROM emulation functionalityVSAvoidsystem cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

By segmenting the Flash memory into first and second regions with different access characteristics, the system achieves EEPROM emulation functionality while reducing the total memory size required. This segmentation strategy directly lowers component costs and system complexity, making the solution more cost-effective compared to conventional uniform allocation schemes.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If data is stored in Flash memory without region separation, then simple storage is achieved, but data management efficiency decreases due to frequent updates requiring copying between sectors

Engineering Contradiction:
Improvestorage structure simplicityVSAvoiddata management efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The storage structure is segmented into first and second regions based on data update frequency. The first region handles quasi-static data with infrequent updates, eliminating the need for frequent copying operations. The second region handles frequently updated data with optimized access patterns. This segmentation significantly improves data management efficiency by reducing copy operations while maintaining reasonable structural complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically manages data storage by directing different types of data to appropriate regions based on their update characteristics. This dynamic allocation strategy optimizes data management efficiency by matching storage location with access patterns, reducing the overhead of copying operations between sectors.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS9389999B2System and method for emulating an EEPROM in a non-volatile memory device
Publication Date: 2016.07.12 INFINEON TECHNOLOGIES AG
  • US9389999B2 patent drawing
  • US9389999B2 patent drawing
  • US9389999B2 patent drawing

AI summary

The invention relates to an electronic memory system, and more specifically, to a system for emulating an electrically erasable programmable read only memory in a non-volatile memory device, and a method of emulating an electrically erasable programmable read only memory in a non-volatile memory device. According to an embodiment, a system for emulating an electrically erasable programmable read only memory is provided, the system including a Flash memory, wherein the Flash memory is configurable into a first region and a second region, wherein the first region is adapted to store a first class of data and the second region is adapted to store a second, different class of data.