Flash Memory Register Switching for Faster Read and Program Cycles
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Solution Overview
Problem
Current flash memory devices, particularly those with MCU architecture, face inefficiencies due to serial operation of circuits over a single bus, leading to prolonged read and program times, which hinder performance and flexibility in modifying control algorithms.
Innovation Solution
Implementing a peripheral circuit with a prime and backup register configuration for each circuit, allowing the MCU to switch between them, enabling simultaneous preparation of configuration parameters for subsequent operations while current operations are being performed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If circuits are operated serially over a single bus in MCU architecture, then device complexity is reduced, but read and program times are prolonged
Solution Approach 1:
The patent divides the control logic into multiple independent circuit blocks, each with its own dedicated bus and register. This segmentation allows parallel operation of multiple circuits simultaneously, reducing the overall read and program times while maintaining manageable device complexity through modular organization.
Solution Approach 2:
The patent transitions from a single-dimension serial bus architecture to a multi-dimension parallel architecture by introducing multiple independent buses operating simultaneously. This dimensional expansion enables concurrent data transmission between the MCU and different circuit blocks, effectively reducing operation times without proportionally increasing complexity.
2Adaptability or versatility
If control algorithms are modified in MCU architecture, then adaptability is improved, but re-fabrication is required which increases manufacturing complexity
Solution Approach 1:
The patent pre-configures multiple dedicated buses and registers during manufacturing, establishing a flexible architectural framework that allows control algorithms to be modified through software or configuration without requiring physical re-fabrication. This preliminary structural preparation enables future adaptability while maintaining current manufacturing simplicity.
3Productivity
If multiple registers are implemented for parallel circuit control, then operational efficiency is improved, but device complexity increases
Solution Approach 1:
The patent implements multiple registers and buses that are designed with uniform structures and identical functions across different circuit blocks. Each register-bus pair operates independently but follows the same design pattern, allowing the system to achieve high operational efficiency through parallelism while managing complexity through design standardization and modularity.
Data Source
AI summary
The present disclosure relates to methods and devices for operating a memory device. In one example, a memory device includes a memory array that includes memory cells, and a peripheral circuit coupled to the memory array. The peripheral circuit includes a micro controller unit (MCU) and a plurality of circuits controlled by the MCU. The MCU is configured to switch between a first register and a second register that are coupled to a first circuit of the plurality of circuits.