On-Chip Flash Memory Repair Circuit Using EEPROM and CAM
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Solution Overview
Problem
Existing integrated circuits with on-chip memory face challenges in efficiently repairing defective memory cells, as current methods require significant resources, are prone to errors, and can only be performed during factory testing, limiting their ability to address defective cells that may arise during the circuit's lifetime.
Innovation Solution
An integrated circuit design that includes a repair controller, a cache memory, and an electrically erasable programmable read-only memory (EEPROM) system, allowing for on-the-fly repair of defective memory cells by transferring data from a flash memory to the EEPROM and using a content-addressable memory (CAM) to ensure accurate data retrieval, eliminating the need for fuses and redundant memory sectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fuses and redundant memory sectors are used to repair defective memory cells, then memory repair capability is achieved, but resource consumption increases and repair reliability decreases due to fuse deactivation errors
Solution Approach 1:
The patent creates a copy of the defective memory sector's data and stores it in a spare memory sector. Instead of using fuses to disable defective cells, the system copies valid data to replacement locations and updates mapping tables, eliminating the need for physical fuse deactivation and redundant hardware structures.
Solution Approach 2:
The patent introduces a mapping table as an intermediary layer between the memory controller and physical memory cells. This mapping table stores the correspondence between logical addresses and physical memory locations, allowing the system to redirect access away from defective cells without requiring complex fuse programming or redundant memory structures.
2Ease of manufacture
If fuses are used for memory repair, then defective sectors can be disabled, but the process requires external components like lasers and can only be performed during factory testing
Solution Approach 1:
The patent replaces the mechanical/optical fuse deactivation process (requiring lasers) with an electrical/software-based solution. The mapping table is updated through electrical writes to memory cells, allowing repair operations to be performed using standard memory interfaces without external laser equipment.
Solution Approach 2:
The patent pre-allocates spare memory sectors and maintains a mapping table that can be dynamically updated. This preliminary preparation allows repair operations to be executed quickly by simply updating the mapping table, rather than performing time-consuming fuse deactivation processes during repair.
3Reliability
If redundant rows or columns are used in repair circuits, then defective cells can be substituted, but additional processing time is required to determine and substitute rows or columns
Solution Approach 1:
The patent copies the functionality of entire rows or columns into compact mapping table entries that store only the necessary address translation information. This allows the system to redirect access to spare memory locations without requiring complex row/column substitution logic, significantly reducing processing time.
Data Source
Figure 1
AI summary
An integrated circuit includes on-chip flash memory, a EEPROM, cache memory, and a repair controller. When a defective address is detected in the flash memory, data slotted to be stored at the defective address is stored in the EEPROM by the repair controller. The cache memory includes a content addressable memory (CAM) that checks read addresses with the defective memory address and if there is a match, the data stored in the EEPROM is moved to the cache so that it can be output in place of data stored at the defective location of the flash memory. The memory repair system does not require any fuses nor is the flash required to include redundant rows or columns. Further, defective addresses can be detected and repaired on-the-fly.