Flash Memory Replication Interface for Parallel Data Access
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Solution Overview
Problem
Conventional data processing systems are inefficient in handling petabyte-scale data sets, leading to impractical analysis due to limited high-bandwidth access and parallel processing capabilities.
Innovation Solution
A scalable data processing system architecture featuring multiple CPU subsystems, memory complexes, and an Ethernet switch fabric, with cache coherence mechanisms and software-implemented flash translation layer policies, enabling efficient parallel access and management of large data sets across interconnected memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional data processing systems are used, then system simplicity is maintained, but high-bandwidth access to petabyte-scale data sets is insufficient
Solution Approach 1:
The system divides the data processing architecture into multiple CPU subsystems, each with its own memory controller and memory complex, interconnected through an Ethernet switch fabric. This segmentation allows petabyte-scale data sets to be distributed across multiple memory complexes while maintaining high-bandwidth access through parallel processing paths.
Solution Approach 2:
The patent introduces a new dimensional aspect by implementing multi-threaded operations across multiple CPU subsystems simultaneously. The Ethernet switch fabric enables data to flow through multiple dimensions (parallel paths) rather than a single sequential path, achieving high-bandwidth access to petabyte-scale data sets.
2Productivity
If multiple CPU subsystems and memory complexes are interconnected, then parallel processing capability increases, but system complexity increases
Solution Approach 1:
The Ethernet switch fabric serves multiple functions: it interconnects CPU subsystems to memory complexes, provides cache coherence mechanisms, and enables software-implemented flash translation layer policies. This multi-functionality reduces the need for separate dedicated components, thereby managing system complexity while maintaining high parallel processing throughput.
Solution Approach 2:
The Ethernet switch fabric acts as an intermediary between CPU subsystems and memory complexes, managing the complexity of interconnections through standardized Ethernet protocols. This intermediary layer simplifies the overall system architecture by providing a universal communication interface rather than requiring direct point-to-point connections between all components.
3Quantity of substance
If flash memory devices are used for large data sets, then storage capacity increases, but data access speed decreases
Solution Approach 1:
The system implements preliminary actions by using cache coherence mechanisms to pre-load and pre-position data in memory complexes before it is needed for processing. The software-implemented flash translation layer also performs preliminary data preparation and optimization, reducing the access time when data is retrieved from flash memory devices.
Solution Approach 2:
The patent ensures continuous useful action by maintaining data in the memory complex and cache hierarchies between access cycles. The Ethernet switch fabric enables continuous data flow between memory complexes and CPU subsystems, reducing idle time and maintaining high access speeds even when dealing with large flash memory capacities.
Data Source
AI summary
According to one embodiment, a data processing system includes a plurality of central processing unit (CPU) subsystems, each CPU subsystem having a plurality of CPUs and a plurality of memory controllers, each memory controller corresponding to one of the CPUs, a plurality of memory complexes, each memory complex being associated with one of the CPU subsystems, wherein each memory complex comprises one or more branches, a plurality of memory leaves to store data, wherein each of the branches is coupled to one or more of the memory leaves and to provide access to the data stored in the memory leaves, and a replication interface to automatically replicate data received from one of the CPU subsystems to another one of the memory complexes, wherein the received data is to be stored in one of the memory leaves.